From: Samuel Pitoiset Date: Wed, 2 Aug 2023 06:54:43 +0000 (+0200) Subject: radv: assume a TCS needs an epilog unless it's linked with a TES X-Git-Tag: upstream/23.3.3~4796 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=54a6eb6613a298aba64554f3292fdf024271d703;p=platform%2Fupstream%2Fmesa.git radv: assume a TCS needs an epilog unless it's linked with a TES For shader object. Signed-off-by: Samuel Pitoiset Part-of: --- diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 4ac4692..19613c0 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -489,6 +489,9 @@ gather_shader_info_tcs(struct radv_device *device, const nir_shader *nir, const nir->info.tess.tcs_vertices_out, info->tcs.num_linked_inputs, info->num_tess_patches, info->tcs.num_linked_outputs, info->tcs.num_linked_patch_outputs); } + + /* By default, assume a TCS needs an epilog unless it's linked with a TES. */ + info->has_epilog = true; } static void @@ -1607,6 +1610,7 @@ radv_link_shaders_info(struct radv_device *device, struct radv_shader_stage *pro struct radv_shader_stage *tcs_stage = producer; struct radv_shader_stage *tes_stage = consumer; + tcs_stage->info.has_epilog = false; tcs_stage->info.tcs.tes_reads_tess_factors = !!(tes_stage->nir->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER)); tcs_stage->info.tcs.tes_inputs_read = tes_stage->nir->info.inputs_read;