From: Kito Cheng <kito.cheng@sifive.com>
Date: Mon, 22 Mar 2021 08:32:45 +0000 (+0800)
Subject: PR target/99702: Check RTL type before get value
X-Git-Tag: upstream/12.2.0~9195
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=540dace2ed3949571f2ce6cb007354e69bda0cb2;p=platform%2Fupstream%2Fgcc.git

PR target/99702: Check RTL type before get value

gcc/ChangeLog:

	PR target/99702
	* config/riscv/riscv.c (riscv_expand_block_move): Get RTL value
	after type checking.

gcc/testsuite/ChangeLog:

	PR target/99702
	* gcc.target/riscv/pr99702.c: New.
---

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 96fc0c0..de8308c 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -3259,9 +3259,9 @@ riscv_block_move_loop (rtx dest, rtx src, unsigned HOST_WIDE_INT length,
 bool
 riscv_expand_block_move (rtx dest, rtx src, rtx length)
 {
-  unsigned HOST_WIDE_INT hwi_length = UINTVAL (length);
   if (CONST_INT_P (length))
     {
+      unsigned HOST_WIDE_INT hwi_length = UINTVAL (length);
       unsigned HOST_WIDE_INT factor, align;
 
       align = MIN (MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), BITS_PER_WORD);
diff --git a/gcc/testsuite/gcc.target/riscv/pr99702.c b/gcc/testsuite/gcc.target/riscv/pr99702.c
new file mode 100644
index 0000000..a28724c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr99702.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+char n;
+void *i, *j;
+void foo(void) {
+  __builtin_memcpy(i, j, n);
+}