From: Geert Uytterhoeven Date: Mon, 2 May 2022 12:35:02 +0000 (+0200) Subject: clk: renesas: r9a07g044: Fix OSTM1 module clock name X-Git-Tag: v6.6.17~7417^2~3^5^2~9 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=53c58c08b454aea3c9c9ceda600567436134e6a2;p=platform%2Fkernel%2Flinux-rpi.git clk: renesas: r9a07g044: Fix OSTM1 module clock name Fix a typo in the name of the "ostm1_pclk" clock. This change has no run-time impact. Fixes: 161450134ae9bab3 ("clk: renesas: r9a07g044: Add OSTM clock and reset entries") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/e0eff1f57378ec29d0d3f1a7bdd7e380583f736b.1651494871.git.geert+renesas@glider.be --- diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 57ec506..0a5c226 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -212,7 +212,7 @@ static const struct { 0x52c, 1), DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0, 0x534, 0), - DEF_MOD("ostm1_clk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0, + DEF_MOD("ostm1_pclk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0, 0x534, 1), DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, 0x534, 2),