From: Sylwester Nawrocki Date: Wed, 4 Nov 2020 10:36:55 +0000 (+0100) Subject: ARM: dts: exynos: Add interconnect properties to Exynos4412 bus nodes X-Git-Tag: v5.15~2144^2~18^2~19 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=5334df3a4bc50f422684291d045aa2c821d7ff0b;p=platform%2Fkernel%2Flinux-starfive.git ARM: dts: exynos: Add interconnect properties to Exynos4412 bus nodes This patch adds the following properties for Exynos4412 interconnect bus nodes: - interconnects: to declare connections between nodes in order to guarantee PM QoS requirements between nodes, - #interconnect-cells: required by the interconnect framework, - samsung,data-clk-ratio: which allows to specify minimum data clock frequency corresponding to requested bandwidth for each bus. Note that #interconnect-cells is always zero and node IDs are not hardcoded anywhere. Signed-off-by: Artur Świgoń Signed-off-by: Sylwester Nawrocki Tested-by: Chanwoo Choi Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20201104103657.18007-6-s.nawrocki@samsung.com Signed-off-by: Krzysztof Kozlowski --- diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index fa8e8d6..05e2156 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -383,6 +383,8 @@ clocks = <&clock CLK_DIV_DMC>; clock-names = "bus"; operating-points-v2 = <&bus_dmc_opp_table>; + samsung,data-clock-ratio = <4>; + #interconnect-cells = <0>; status = "disabled"; }; @@ -450,6 +452,8 @@ clocks = <&clock CLK_DIV_GDL>; clock-names = "bus"; operating-points-v2 = <&bus_leftbus_opp_table>; + interconnects = <&bus_dmc>; + #interconnect-cells = <0>; status = "disabled"; }; @@ -466,6 +470,8 @@ clocks = <&clock CLK_ACLK160>; clock-names = "bus"; operating-points-v2 = <&bus_display_opp_table>; + interconnects = <&bus_leftbus &bus_dmc>; + #interconnect-cells = <0>; status = "disabled"; };