From: Alexander Stein Date: Wed, 30 Nov 2016 16:34:15 +0000 (+0100) Subject: i2c: designware-pcidrv: Add 10bit address feature to medfield/merrifield X-Git-Tag: v4.14-rc1~1864^2~8 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=531ccabbe4cc2d09234e9009d47f7f2539c6d047;p=platform%2Fkernel%2Flinux-rpi.git i2c: designware-pcidrv: Add 10bit address feature to medfield/merrifield Both Merrifield TRM and Medfield TRM state: "Both 7-bit and 10-bit addressing modes are supported." Signed-off-by: Alexander Stein Acked-by: Andy Shevchenko Acked-by: Jarkko Nikula Signed-off-by: Wolfram Sang --- diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c index 300802e..d6423cf 100644 --- a/drivers/i2c/busses/i2c-designware-pcidrv.c +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c @@ -141,6 +141,7 @@ static struct dw_pci_controller dw_pci_controllers[] = { .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, .tx_fifo_depth = 32, .rx_fifo_depth = 32, + .functionality = I2C_FUNC_10BIT_ADDR, .clk_khz = 25000, .setup = mfld_setup, }, @@ -149,6 +150,7 @@ static struct dw_pci_controller dw_pci_controllers[] = { .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST, .tx_fifo_depth = 64, .rx_fifo_depth = 64, + .functionality = I2C_FUNC_10BIT_ADDR, .scl_sda_cfg = &mrfld_config, .setup = mrfld_setup, },