From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: Tue, 27 Mar 2012 15:41:55 +0000 (+0100)
Subject: PPC: Fix TLB invalidation bug within the PPC interrupt handler.
X-Git-Tag: TizenStudio_2.0_p2.3.2~208^2~4239^2~19
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=52d631dcc70144b6ce8293db78cd6de635331c83;p=sdk%2Femulator%2Fqemu.git

PPC: Fix TLB invalidation bug within the PPC interrupt handler.

Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLB
flush bug. By applying a mask to the interrupt MSR which cleared the IR/DR
bits at the start of the interrupt handler, the logic towards the end of the
handler to force a TLB flush if either one of these bits were set would never
be triggered.

This patch simply changes the IR/DR bit check in the TLB flush logic to use
the original MSR value (albeit with some interrupt-specific bits cleared) so
that the IR/DR bits are preserved at the point where the check takes place.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---

diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index e13b749..f0ea1c3 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -2960,7 +2960,7 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
     if (asrr1 != -1)
         env->spr[asrr1] = env->spr[srr1];
     /* If we disactivated any translation, flush TLBs */
-    if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR)))
+    if (msr & ((1 << MSR_IR) | (1 << MSR_DR)))
         tlb_flush(env, 1);
 
     if (msr_ile) {