From: Kuogee Hsieh Date: Thu, 9 Sep 2021 19:49:58 +0000 (-0700) Subject: arm64: dts: qcom: sc7280: fix display port phy reg property X-Git-Tag: accepted/tizen/unified/20230118.172025~5476 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=52a994c15a9a7bcdb92336dc9a68a898e8d99907;p=platform%2Fkernel%2Flinux-rpi.git arm64: dts: qcom: sc7280: fix display port phy reg property [ Upstream commit 425f30cc843c727bc7753a0d33710d1e4a999168 ] Existing display port phy reg property is derived from usb phy which map display port phy pcs to wrong address which cause aux init with wrong address and prevent both dpcd read and write from working. Fix this problem by assigning correct pcs address to display port phy reg property. Fixes: bb9efa59c665 ("arm64: dts: qcom: sc7280: Add USB related nodes") Signed-off-by: Kuogee Hsieh Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631216998-10049-1-git-send-email-khsieh@codeaurora.org Signed-off-by: Sasha Levin --- diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index fd78f16..f583365 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1258,15 +1258,11 @@ dp_phy: dp-phy@88ea200 { reg = <0 0x088ea200 0 0x200>, <0 0x088ea400 0 0x200>, - <0 0x088eac00 0 0x400>, + <0 0x088eaa00 0 0x200>, <0 0x088ea600 0 0x200>, - <0 0x088ea800 0 0x200>, - <0 0x088eaa00 0 0x100>; + <0 0x088ea800 0 0x200>; #phy-cells = <0>; #clock-cells = <1>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; }; };