From: Peter Horton Date: Sun, 29 Jan 2006 21:33:48 +0000 (+0000) Subject: [MIPS] Fix Cobalt PCI cache line sizes X-Git-Tag: v2.6.16-rc3~137^2~18 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=52378445da0253d5031590e5e9186ee448dc0b4a;p=platform%2Fkernel%2Flinux-exynos.git [MIPS] Fix Cobalt PCI cache line sizes Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index b664df1..75a01e7 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c @@ -52,7 +52,7 @@ static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) pci_read_config_byte(dev, PCI_LATENCY_TIMER, <); if (lt < 64) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); - pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, @@ -69,7 +69,7 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev) * host bridge. */ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); - pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); /* * The code described by the comment below has been removed