From: Marek Olšák Date: Sat, 25 Feb 2023 22:06:06 +0000 (-0500) Subject: radeonsi: add si_pm4_set_reg_va to simplify setting reg_va_low_idx for RGP X-Git-Tag: upstream/23.3.3~12285 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=51e4437eee19bc8f289cf140e0217d105a327603;p=platform%2Fupstream%2Fmesa.git radeonsi: add si_pm4_set_reg_va to simplify setting reg_va_low_idx for RGP Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c index 635d4aa..8e2b36e 100644 --- a/src/gallium/drivers/radeonsi/si_pm4.c +++ b/src/gallium/drivers/radeonsi/si_pm4.c @@ -114,6 +114,12 @@ void si_pm4_set_reg_idx3(struct si_screen *sscreen, struct si_pm4_state *state, sscreen->info.gfx_level >= GFX10 ? 3 : 0); } +void si_pm4_set_reg_va(struct si_pm4_state *state, unsigned reg, uint32_t val) +{ + si_pm4_set_reg(state, reg, val); + state->reg_va_low_idx = state->ndw - 1; +} + void si_pm4_clear_state(struct si_pm4_state *state) { state->ndw = 0; diff --git a/src/gallium/drivers/radeonsi/si_pm4.h b/src/gallium/drivers/radeonsi/si_pm4.h index ac73a32..0f3725e 100644 --- a/src/gallium/drivers/radeonsi/si_pm4.h +++ b/src/gallium/drivers/radeonsi/si_pm4.h @@ -66,6 +66,7 @@ struct si_pm4_state { void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw); void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val); +void si_pm4_set_reg_va(struct si_pm4_state *state, unsigned reg, uint32_t val); void si_pm4_set_reg_idx3(struct si_screen *sscreen, struct si_pm4_state *state, unsigned reg, uint32_t val); diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index 09dd033..0ad0301 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -688,8 +688,7 @@ static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader) return; va = shader->bo->gpu_address; - si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); - pm4->reg_va_low_idx = pm4->ndw - 1; + si_pm4_set_reg_va(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) | @@ -719,11 +718,10 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader) C_00B404_CU_EN, 16, &sscreen->info)); } if (sscreen->info.gfx_level >= GFX10) { - si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); + si_pm4_set_reg_va(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8); } else { - si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8); + si_pm4_set_reg_va(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8); } - pm4->reg_va_low_idx = pm4->ndw - 1; unsigned num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR); @@ -735,8 +733,7 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader) else shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5); } else { - si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8); - pm4->reg_va_low_idx = pm4->ndw - 1; + si_pm4_set_reg_va(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8); si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(sscreen->info.address32_hi >> 8)); @@ -811,8 +808,7 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader) oc_lds_en = shader->selector->stage == MESA_SHADER_TESS_EVAL ? 1 : 0; - si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); - pm4->reg_va_low_idx = pm4->ndw - 1; + si_pm4_set_reg_va(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(sscreen->info.address32_hi >> 8)); si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES, @@ -1078,11 +1074,10 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) num_user_sgprs = GFX9_GS_NUM_USER_SGPR; if (sscreen->info.gfx_level >= GFX10) { - si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); + si_pm4_set_reg_va(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); } else { - si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8); + si_pm4_set_reg_va(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8); } - pm4->reg_va_low_idx = pm4->ndw - 1; uint32_t rsrc1 = S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) | S_00B228_MEM_ORDERED(si_shader_mem_ordered(shader)) | @@ -1132,8 +1127,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) S_00B21C_WAVE_LIMIT(0x3F), C_00B21C_CU_EN, 0, &sscreen->info); - si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8); - pm4->reg_va_low_idx = pm4->ndw - 1; + si_pm4_set_reg_va(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8); si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(sscreen->info.address32_hi >> 8)); @@ -1389,8 +1383,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader shader->config.scratch_bytes_per_wave > 0, &late_alloc_wave64, &cu_mask); - si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); - pm4->reg_va_low_idx = pm4->ndw - 1; + si_pm4_set_reg_va(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); si_pm4_set_reg( pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, S_00B228_VGPRS((shader->config.num_vgprs - 1) / (shader->wave_size == 32 ? 8 : 4)) | @@ -1709,8 +1702,7 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader, si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(late_alloc_wave64)); } - si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8); - pm4->reg_va_low_idx = pm4->ndw - 1; + si_pm4_set_reg_va(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8); si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(sscreen->info.address32_hi >> 8)); @@ -2000,8 +1992,7 @@ static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader) shader->ps.cb_shader_mask = cb_shader_mask; va = shader->bo->gpu_address; - si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8); - pm4->reg_va_low_idx = pm4->ndw - 1; + si_pm4_set_reg_va(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8); si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(sscreen->info.address32_hi >> 8));