From: Dharageswari R Date: Fri, 3 Jun 2016 12:59:37 +0000 (+0530) Subject: ASoC: Intel: Skylake: Disable SRAM Retention before D3 X-Git-Tag: v4.14-rc1~2705^2~7^2~14^2~45 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=51a01b8c2ea632ed9a57f98c234a0cd9dafe181a;p=platform%2Fkernel%2Flinux-rpi.git ASoC: Intel: Skylake: Disable SRAM Retention before D3 SW needs to set the PGCTL.LSRMD = 1 to disable LPSRAM retention feature,otherwise it may lead to SRAM ECC Errors. Signed-off-by: Dharageswari R Signed-off-by: Jeeja KP Signed-off-by: Vinod Koul Signed-off-by: Mark Brown --- diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c index 55c301b..cb3eb41 100644 --- a/sound/soc/intel/skylake/skl.c +++ b/sound/soc/intel/skylake/skl.c @@ -186,6 +186,7 @@ static int _skl_suspend(struct hdac_ext_bus *ebus) { struct skl *skl = ebus_to_skl(ebus); struct hdac_bus *bus = ebus_to_hbus(ebus); + struct pci_dev *pci = to_pci_dev(bus->dev); int ret; snd_hdac_ext_bus_link_power_down_all(ebus); @@ -195,6 +196,8 @@ static int _skl_suspend(struct hdac_ext_bus *ebus) return ret; snd_hdac_bus_stop_chip(bus); + update_pci_dword(pci, AZX_PCIREG_PGCTL, + AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK); skl_enable_miscbdcge(bus->dev, false); snd_hdac_bus_enter_link_reset(bus); skl_enable_miscbdcge(bus->dev, true); diff --git a/sound/soc/intel/skylake/skl.h b/sound/soc/intel/skylake/skl.h index f66be17..25b8d48 100644 --- a/sound/soc/intel/skylake/skl.h +++ b/sound/soc/intel/skylake/skl.h @@ -48,6 +48,8 @@ #define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094 #define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20 +#define AZX_PCIREG_PGCTL 0x44 +#define AZX_PGCTL_LSRMD_MASK (1 << 4) #define AZX_PCIREG_CGCTL 0x48 #define AZX_CGCTL_MISCBDCGE_MASK (1 << 6)