From: Daniel Vetter Date: Tue, 10 Nov 2020 12:58:05 +0000 (+0100) Subject: Merge v5.10-rc3 into drm-next X-Git-Tag: v5.15~2259^2~11 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=512bce50a41c528fa15c4c014293e7bebf018658;p=platform%2Fkernel%2Flinux-starfive.git Merge v5.10-rc3 into drm-next We need commit f8f6ae5d077a ("mm: always have io_remap_pfn_range() set pgprot_decrypted()") to be able to merge Jason's cleanup patch. Signed-off-by: Daniel Vetter --- 512bce50a41c528fa15c4c014293e7bebf018658 diff --cc drivers/gpu/drm/amd/display/include/dal_asic_id.h index 33128eb,ffcb059..24346f1 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@@ -203,20 -202,13 +203,24 @@@ enum #define ASICREV_IS_NAVI12_P(eChipRev) ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0)) #define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN)) #define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0)) -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) -#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0)) +#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0) && (eChipRev < NV_DIMGREY_CAVEFISH_P_A0)) +#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev) ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_UNKNOWN)) +#define GREEN_SARDINE_A0 0xA1 +#ifndef ASICREV_IS_GREEN_SARDINE +#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF)) +#endif +#define FAMILY_VGH 144 +#define DEVICE_ID_VGH_163F 0x163F +#define VANGOGH_A0 0x01 +#define VANGOGH_UNKNOWN 0xFF + +#ifndef ASICREV_IS_VANGOGH +#define ASICREV_IS_VANGOGH(eChipRev) ((eChipRev >= VANGOGH_A0) && (eChipRev < VANGOGH_UNKNOWN)) #endif + #define GREEN_SARDINE_A0 0xA1 + #ifndef ASICREV_IS_GREEN_SARDINE + #define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF)) + #endif /* * ASIC chip ID