From: Craig Topper Date: Mon, 27 Mar 2023 17:06:34 +0000 (-0700) Subject: foo X-Git-Tag: upstream/17.0.6~13556 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4fde20b8a62ed3d850e4e770ae640039ca1a9ed8;p=platform%2Fupstream%2Fllvm.git foo --- diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 07728c7..108ecf8 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -1505,7 +1505,7 @@ RISCVAsmParser::parseInsnDirectiveOpcode(OperandVector &Operands) { auto *CE = dyn_cast(Res); if (CE) { int64_t Imm = CE->getValue(); - if (isUInt<7>(Imm) && (Imm & 3) == 3) { + if (isUInt<7>(Imm)) { Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64())); return MatchOperand_Success; } @@ -1534,8 +1534,8 @@ RISCVAsmParser::parseInsnDirectiveOpcode(OperandVector &Operands) { break; } - Error(S, "opcode must be in the range [0, 127] and the lower 2 bits must be " - "0x3"); + Error(S, "opcode must be a valid opcode name or an immediate in the range " + "[0, 127]"); return MatchOperand_ParseFail; } diff --git a/llvm/test/MC/RISCV/insn-invalid.s b/llvm/test/MC/RISCV/insn-invalid.s index ab41f07..82fdd7b 100644 --- a/llvm/test/MC/RISCV/insn-invalid.s +++ b/llvm/test/MC/RISCV/insn-invalid.s @@ -14,8 +14,7 @@ .insn q 0x13, 0, a0, a1, 13, 14 # CHECK: :[[@LINE]]:7: error: invalid instruction format # Invalid immediate -.insn i 0x99, 0, a0, 4(a1) # CHECK: :[[@LINE]]:10: error: opcode must be in the range [0, 127] and the lower 2 bits must be 0x3 -.insn i 0, 0, a0, 4(a1) # CHECK: :[[@LINE]]:10: error: opcode must be in the range [0, 127] and the lower 2 bits must be 0x3 +.insn i 0x99, 0, a0, 4(a1) # CHECK: :[[@LINE]]:10: error: opcode must be in the range [0, 127] .insn r 0x33, 8, 0, a0, a1, a2 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 7] .insn r4 0x43, 0, 4, fa0, fa1, fa2, fa3 # CHECK: :[[@LINE]]:21: error: immediate must be an integer in the range [0, 3]