From: Ezequiel Garcia Date: Tue, 26 May 2015 22:01:07 +0000 (-0300) Subject: clk: pistachio: Add a pll_lock() helper for clarity X-Git-Tag: v4.2~211^2~30^2~20 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4f4adfbf8e655914bb80daa0252c90b62fd27d78;p=platform%2Fkernel%2Flinux-amlogic.git clk: pistachio: Add a pll_lock() helper for clarity This commit adds a pll_lock() helper making the code more readable. Cosmetic change only, no functionality changes. Signed-off-by: Andrew Bresticker Signed-off-by: Ezequiel Garcia Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/pistachio/clk-pll.c b/drivers/clk/pistachio/clk-pll.c index de53756..9ce1be7 100644 --- a/drivers/clk/pistachio/clk-pll.c +++ b/drivers/clk/pistachio/clk-pll.c @@ -67,6 +67,12 @@ static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg) writel(val, pll->base + reg); } +static inline void pll_lock(struct pistachio_clk_pll *pll) +{ + while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK)) + cpu_relax(); +} + static inline u32 do_div_round_closest(u64 dividend, u32 divisor) { dividend += divisor / 2; @@ -178,8 +184,7 @@ static int pll_gf40lp_frac_set_rate(struct clk_hw *hw, unsigned long rate, (params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT); pll_writel(pll, val, PLL_CTRL2); - while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK)) - cpu_relax(); + pll_lock(pll); if (!was_enabled) pll_gf40lp_frac_disable(hw); @@ -288,8 +293,7 @@ static int pll_gf40lp_laint_set_rate(struct clk_hw *hw, unsigned long rate, (params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT); pll_writel(pll, val, PLL_CTRL1); - while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK)) - cpu_relax(); + pll_lock(pll); if (!was_enabled) pll_gf40lp_laint_disable(hw);