From: Marek Olšák Date: Fri, 27 Jan 2023 05:33:41 +0000 (-0500) Subject: amd: define new SET_*_REG_PAIRS packets X-Git-Tag: upstream/23.3.3~13604 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4f246f27b1f7ef0876a9b2cf6cb641df30ceeba4;p=platform%2Fupstream%2Fmesa.git amd: define new SET_*_REG_PAIRS packets Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index f6e8022..47665e2 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -1412,6 +1412,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info) /* The size must be aligned to 64K per SE and must be at most 16M in total. */ info->attribute_ring_size_per_se = align(info->attribute_ring_size_per_se, 64 * 1024); assert(info->attribute_ring_size_per_se * info->max_se <= 16 * 1024 * 1024); + + info->has_set_reg_pairs = info->pfp_fw_version >= SET_REG_PAIRS_PFP_VERSION; + info->has_set_sh_reg_pairs_n = info->pfp_fw_version >= SET_REG_PAIRS_PACKED_N_COUNT14_PFP_VERSION; } set_custom_cu_en_mask(info); @@ -1600,6 +1603,8 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f) fprintf(f, " mec_fw_feature = %i\n", info->mec_fw_feature); fprintf(f, " pfp_fw_version = %i\n", info->pfp_fw_version); fprintf(f, " pfp_fw_feature = %i\n", info->pfp_fw_feature); + fprintf(f, " has_set_reg_pairs = %i\n", info->has_set_reg_pairs); + fprintf(f, " has_set_sh_reg_pairs_n = %i\n", info->has_set_sh_reg_pairs_n); fprintf(f, "Multimedia info:\n"); fprintf(f, " vce_encode = %u\n", info->ip[AMD_IP_VCE].num_queues); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 4b72c4b..0894925 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -165,6 +165,8 @@ struct radeon_info { uint32_t mec_fw_feature; uint32_t pfp_fw_version; uint32_t pfp_fw_feature; + bool has_set_reg_pairs; + bool has_set_sh_reg_pairs_n; /* Multimedia info. */ struct { diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h index 66f507d..c2b8816 100644 --- a/src/amd/common/sid.h +++ b/src/amd/common/sid.h @@ -254,6 +254,31 @@ #define PKT3_DISPATCH_TASKMESH_INDIRECT_MULTI_ACE 0xAD /* Indirect task+mesh shader dispatch [ACE side] */ #define PKT3_EVENT_WRITE_ZPASS 0xB1 /* GFX11+ & PFP version >= 1458 */ #define EVENT_WRITE_ZPASS_PFP_VERSION 1458 +/* All PAIRS packets require GFX11+ and PFP version >= 1448. + * + * SET_CONTEXT_REG_PAIRS: + * SET_SH_REG_PAIRS: + * Format: header, (offset, value)^n. + * Consecutive offsets must not be equal. Not recommended because the PACKED variants are better. + * + * SET_CONTEXT_REG_PAIRS_PACKED: + * SET_SH_REG_PAIRS_PACKED: + * SET_SH_REG_PAIRS_PACKED_N: + * Format: header, count, (offset0 | (offset1 << 16), value0, value1)^(count / 2) + * Consecutive offsets must not be equal. "count" is the register count and must be aligned to 2. + * If the register count is odd, it's recommended to duplicate the first register in the last register. + * The SH_*_PACKED* variants require register shadowing to be enabled. The *_N variant is + * identical to the non-N variant, but is faster with the following limitation: + * If PFP version >= 1463, "count" must be at most 14, else "count" must be at most 8. If "count" + * is greater than the limit, use the non-N variant. + */ +#define PKT3_SET_CONTEXT_REG_PAIRS 0xB8 /* GFX11+, PFP version >= 1448 */ +#define PKT3_SET_CONTEXT_REG_PAIRS_PACKED 0xB9 /* GFX11+, PFP version >= 1448 */ +#define PKT3_SET_SH_REG_PAIRS 0xBA /* GFX11+, PFP version >= 1448 */ +#define PKT3_SET_SH_REG_PAIRS_PACKED 0xBB /* GFX11+, PFP version >= 1448 */ +#define PKT3_SET_SH_REG_PAIRS_PACKED_N 0xBD /* GFX11+, PFP version >= 1448 */ +#define SET_REG_PAIRS_PFP_VERSION 1448 +#define SET_REG_PAIRS_PACKED_N_COUNT14_PFP_VERSION 1463 #define PKT_TYPE_S(x) (((unsigned)(x)&0x3) << 30) #define PKT_TYPE_G(x) (((x) >> 30) & 0x3)