From: Markos Chandras <markos.chandras@imgtec.com>
Date: Tue, 2 Dec 2014 15:30:19 +0000 (+0000)
Subject: MIPS: mm: c-r4k: Set the correct ISA level
X-Git-Tag: v4.0-rc1~4^2~26^2~22
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4ee486274ec1e63f056c991e2523c32780670d08;p=platform%2Fkernel%2Flinux-exynos.git

MIPS: mm: c-r4k: Set the correct ISA level

The local_r4k_flush_cache_sigtramp function uses the 'cache'
instruction inside an asm block. However, MIPS R6 changed the
opcode for the cache instruction and as a result of which we
need to set the correct ISA level.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index b806deb..7ecee76 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -794,7 +794,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg)
 		__asm__ __volatile__ (
 			".set push\n\t"
 			".set noat\n\t"
-			".set mips3\n\t"
+			".set "MIPS_ISA_LEVEL"\n\t"
 #ifdef CONFIG_32BIT
 			"la	$at,1f\n\t"
 #endif