From: Matthieu CASTET Date: Wed, 19 Feb 2014 05:46:31 +0000 (+0800) Subject: usb: chipidea: need to mask when writting endptflush and endptprime X-Git-Tag: v3.10.33~32 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4ebd08982393e092b7dbcb19b68c7de252c98988;p=platform%2Fkernel%2Flinux-stable.git usb: chipidea: need to mask when writting endptflush and endptprime commit 5bf5dbeda2454296f1984adfbfc8e6f5965ac389 upstream. ENDPTFLUSH and ENDPTPRIME registers are set by software and clear by hardware. There is a bit for each endpoint. When we are setting a bit for an endpoint we should make sure we do not touch other endpoint bit. There is a race condition if the hardware clear the bit between the read and the write in hw_write. Signed-off-by: Peter Chen Signed-off-by: Matthieu CASTET Tested-by: Michael Grzeschik Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c index b501346..f1cab42 100644 --- a/drivers/usb/chipidea/udc.c +++ b/drivers/usb/chipidea/udc.c @@ -103,7 +103,7 @@ static int hw_ep_flush(struct ci13xxx *ci, int num, int dir) do { /* flush any pending transfer */ - hw_write(ci, OP_ENDPTFLUSH, BIT(n), BIT(n)); + hw_write(ci, OP_ENDPTFLUSH, ~0, BIT(n)); while (hw_read(ci, OP_ENDPTFLUSH, BIT(n))) cpu_relax(); } while (hw_read(ci, OP_ENDPTSTAT, BIT(n))); @@ -203,7 +203,7 @@ static int hw_ep_prime(struct ci13xxx *ci, int num, int dir, int is_ctrl) if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num))) return -EAGAIN; - hw_write(ci, OP_ENDPTPRIME, BIT(n), BIT(n)); + hw_write(ci, OP_ENDPTPRIME, ~0, BIT(n)); while (hw_read(ci, OP_ENDPTPRIME, BIT(n))) cpu_relax();