From: Maciej W. Rozycki Date: Tue, 20 Dec 2016 01:53:03 +0000 (+0000) Subject: MIPS16/opcodes: Correct 64-bit macros' ISA membership X-Git-Tag: users/ARM/embedded-binutils-2_28-branch-2017q1~159 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4ebce1a0a5911e71aa2d00932ffb2126ff1f3633;p=external%2Fbinutils.git MIPS16/opcodes: Correct 64-bit macros' ISA membership Limit the DDIV, DDIVU, DREM, DREMU and DSUBU macros to the MIPS III rather than MIPS I ISA. These macros expand to machine code sequences including 64-bit instructions which require a 64-bit ISA. Entries for those instructions are already correctly marked, however the marking is ignored if entries are used in the process of macro expansion rather than directly, making it possible to indirectly produce 64-bit machine code even when output requested has been limited to a 32-bit ISA. opcodes/ * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu" INSN_MACRO entries. gas/ * testsuite/gas/mips/mips16-macro.l: New list test. * testsuite/gas/mips/mips.exp: Run the new test. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 1038be9..c1e0e1e 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,10 @@ 2016-12-20 Maciej W. Rozycki + * testsuite/gas/mips/mips16-macro.l: New list test. + * testsuite/gas/mips/mips.exp: Run the new test. + +2016-12-20 Maciej W. Rozycki + * testsuite/gas/mips/mips16-sdrasp.d: New test. * testsuite/gas/mips/mips16-sdrasp.l: New stderr output. * testsuite/gas/mips/mips16-sdrasp.s: New test source. diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index 8b80200..101b653 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -853,6 +853,7 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "mips16-64" } run_dump_test "mips16-macro" + run_list_test "mips16-macro" "-32 -march=mips1" # Check MIPS16e extensions run_dump_test_arches "mips16e" [mips_arch_list_matching mips32 !micromips \ !mips32r6] diff --git a/gas/testsuite/gas/mips/mips16-macro.l b/gas/testsuite/gas/mips/mips16-macro.l new file mode 100644 index 0000000..7310371 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-macro.l @@ -0,0 +1,12 @@ +.*: Assembler messages: +.*:6: Error: opcode not supported on this processor: mips1 \(mips1\) `ddiv \$4,\$5,\$6' +.*:7: Error: opcode not supported on this processor: mips1 \(mips1\) `ddivu \$5,\$6,\$7' +.*:10: Error: opcode not supported on this processor: mips1 \(mips1\) `drem \$2,\$3,\$4' +.*:11: Error: opcode not supported on this processor: mips1 \(mips1\) `dremu \$3,\$4,\$5' +.*:13: Error: opcode not supported on this processor: mips1 \(mips1\) `dmul \$5,\$6,\$7' +.*:20: Error: opcode not supported on this processor: mips1 \(mips1\) `dsubu \$4,-32767' +.*:21: Error: opcode not supported on this processor: mips1 \(mips1\) `dsubu \$6,6' +.*:22: Error: opcode not supported on this processor: mips1 \(mips1\) `dsubu \$7,32768' +.*:23: Error: opcode not supported on this processor: mips1 \(mips1\) `dsubu \$2,\$4,-16383' +.*:24: Error: opcode not supported on this processor: mips1 \(mips1\) `dsubu \$3,\$7,8' +.*:25: Error: opcode not supported on this processor: mips1 \(mips1\) `dsubu \$4,\$5,16384' diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4d5fae6..2890354 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,6 +1,12 @@ 2016-12-20 Maciej W. Rozycki * mips16-opc.c (mips16_opcodes): Set membership to I3 rather + than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu" + INSN_MACRO entries. + +2016-12-20 Maciej W. Rozycki + + * mips16-opc.c (mips16_opcodes): Set membership to I3 rather than I1 for the SP-relative "sd"/$ra entry (SDRASP minor opcode). diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c index 14d82bf..0c4bb7f 100644 --- a/opcodes/mips16-opc.c +++ b/opcodes/mips16-opc.c @@ -241,9 +241,9 @@ const struct mips_opcode mips16_opcodes[] = {"daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, {"daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 }, {"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 }, -{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I1, 0, 0 }, +{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 }, {"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 }, -{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I1, 0, 0 }, +{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 }, {"div", "0,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 }, {"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 }, {"divu", "0,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 }, @@ -252,9 +252,9 @@ const struct mips_opcode mips16_opcodes[] = {"dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I3, 0, 0 }, {"dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I3, 0, 0 }, {"drem", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 }, -{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I1, 0, 0 }, +{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 }, {"dremu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 }, -{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I1, 0, 0 }, +{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 }, {"dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 }, {"dsll", "x,w,[", 0x3001, 0xf803, WR_1|RD_2, 0, I3, 0, 0 }, {"dsll", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 }, @@ -265,8 +265,8 @@ const struct mips_opcode mips16_opcodes[] = {"dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 }, {"dsrl", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 }, {"dsubu", "z,v,y", 0xe002, 0xf803, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I1, 0, 0 }, +{"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 }, +{"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I3, 0, 0 }, {"exit", "L", 0xed09, 0xff1f, TRAP, 0, I1, 0, 0 }, {"exit", "L", 0xee09, 0xff1f, TRAP, 0, I1, 0, 0 }, {"exit", "", 0xef09, 0xffff, TRAP, 0, I1, 0, 0 },