From: Michel Dänzer Date: Tue, 12 Mar 2013 11:34:37 +0000 (+0100) Subject: radeonsi: Fix off-by-one for maximum vertex element index in some cases X-Git-Tag: mesa-9.2.1~2305 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4dca602521c51a4cb03855bda9c22b5ccc4829c7;p=platform%2Fupstream%2Fmesa.git radeonsi: Fix off-by-one for maximum vertex element index in some cases In cases where the vertex element size is smaller than the vertex buffer stride, the previous calculation could end up 1 too low. This would result in the GPU using index 0 instead of the maximum index for those elements, which would be visible as intermittent distorted triangles. NOTE: This is a candidate for the 9.1 branch. Reviewed-by: Alex Deucher --- diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index f8460b0..1049d2b 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -448,8 +448,14 @@ static void si_vertex_buffer_update(struct r600_context *rctx) si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF); si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(vb->stride))); - si_pm4_sh_data_add(pm4, (vb->buffer->width0 - vb->buffer_offset) / - MAX2(vb->stride, 1)); + if (vb->stride) + /* Round up by rounding down and adding 1 */ + si_pm4_sh_data_add(pm4, + (vb->buffer->width0 - offset - + util_format_get_blocksize(ve->src_format)) / + vb->stride + 1); + else + si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset); si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]); if (!bound[ve->vertex_buffer_index]) {