From: Stephen Boyd <sboyd@codeaurora.org>
Date: Tue, 28 Jul 2015 18:58:26 +0000 (-0700)
Subject: Merge branch 'for-4.2/ti-clk-move' of https://github.com/t-kristo/linux-pm into clk... 
X-Git-Tag: v4.3-rc2~4^2~107
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4d341056202a4725777ed99897f6456405819cd4;p=platform%2Fkernel%2Flinux-exynos.git

Merge branch 'for-4.2/ti-clk-move' of https://github.com/t-kristo/linux-pm into clk-next

From Tero Kristo:
  "This pull request contains the TI clock driver set to move the
   clock implementations under clock driver. Some small portions of
   the clock driver code still remain under mach-omap2 after this,
   it should be decided whether this code is now obsolete and should
   be deleted or should someone try to fix it."

Slight merge conflicts with determine_rate prototype changes.
---

4d341056202a4725777ed99897f6456405819cd4
diff --cc drivers/clk/ti/clock.h
index 404158d,d4d232fd..d8aafd3
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@@ -169,4 -198,88 +198,80 @@@ void ti_clk_patch_legacy_clks(struct ti
  struct clk *ti_clk_register_clk(struct ti_clk *setup);
  int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
  
+ void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
+ void ti_dt_clocks_register(struct ti_dt_clk *oclks);
+ int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
+ 		      ti_of_clk_init_cb_t func);
+ int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
+ 
+ void omap2_init_clk_hw_omap_clocks(struct clk *clk);
+ int of_ti_clk_autoidle_setup(struct device_node *node);
+ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
+ 
+ extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
+ extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
+ extern const struct clk_hw_omap_ops clkhwops_wait;
+ extern const struct clk_hw_omap_ops clkhwops_iclk;
+ extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
+ extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
+ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
+ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
+ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
+ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
+ extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
+ extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
+ 
+ extern const struct clk_ops ti_clk_divider_ops;
+ extern const struct clk_ops ti_clk_mux_ops;
+ 
+ int omap2_clkops_enable_clkdm(struct clk_hw *hw);
+ void omap2_clkops_disable_clkdm(struct clk_hw *hw);
+ 
+ int omap2_dflt_clk_enable(struct clk_hw *hw);
+ void omap2_dflt_clk_disable(struct clk_hw *hw);
+ int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
+ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
+ 				   void __iomem **other_reg,
+ 				   u8 *other_bit);
+ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
+ 				void __iomem **idlest_reg,
+ 				u8 *idlest_bit, u8 *idlest_val);
+ 
+ void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
+ void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
+ 
+ u8 omap2_init_dpll_parent(struct clk_hw *hw);
+ int omap3_noncore_dpll_enable(struct clk_hw *hw);
+ void omap3_noncore_dpll_disable(struct clk_hw *hw);
+ int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
+ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
+ 				unsigned long parent_rate);
+ int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
+ 					   unsigned long rate,
+ 					   unsigned long parent_rate,
+ 					   u8 index);
 -long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
 -				       unsigned long rate,
 -				       unsigned long min_rate,
 -				       unsigned long max_rate,
 -				       unsigned long *best_parent_rate,
 -				       struct clk_hw **best_parent_clk);
++int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
++				      struct clk_rate_request *req);
+ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
+ 			   unsigned long *parent_rate);
+ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
+ 				    unsigned long parent_rate);
+ 
+ unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
+ int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
+ 			 unsigned long parent_rate);
+ int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
+ 				    unsigned long parent_rate, u8 index);
+ void omap3_clk_lock_dpll5(void);
+ 
+ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
+ 					 unsigned long parent_rate);
+ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
+ 				    unsigned long target_rate,
+ 				    unsigned long *parent_rate);
 -long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
 -					unsigned long rate,
 -					unsigned long min_rate,
 -					unsigned long max_rate,
 -					unsigned long *best_parent_rate,
 -					struct clk_hw **best_parent_clk);
++int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
++				       struct clk_rate_request *req);
+ 
+ extern struct ti_clk_ll_ops *ti_clk_ll_ops;
+ 
  #endif