From: Ben Widawsky <ben@bwidawsk.net>
Date: Wed, 25 Apr 2012 20:33:17 +0000 (-0700)
Subject: chipset updates
X-Git-Tag: 1.3~105
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4d053f97db7759c51c2299b401e166b09efad87e;p=profile%2Fextras%2Fintel-gpu-tools.git

chipset updates

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---

diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 668bf59..bfb1923 100755
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -78,11 +78,18 @@
 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126
 #define PCI_CHIP_SANDYBRIDGE_S		0x010A /* server */
 
-#define PCI_CHIP_IVYBRIDGE_GT1	0x0152 /* desktop */
-#define PCI_CHIP_IVYBRIDGE_GT2	0x0162
+#define PCI_CHIP_IVYBRIDGE_GT1		0x0152 /* desktop */
+#define PCI_CHIP_IVYBRIDGE_GT2		0x0162
 #define PCI_CHIP_IVYBRIDGE_M_GT1	0x0156 /* mobile */
 #define PCI_CHIP_IVYBRIDGE_M_GT2	0x0166
 #define PCI_CHIP_IVYBRIDGE_S		0x015a /* server */
+#define PCI_CHIP_IVYBRIDGE_S_GT2	0x016a /* server */
+
+#define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
+#define PCI_CHIP_HASWELL_GT2            0x0412
+#define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
+#define PCI_CHIP_HASWELL_M_GT2          0x0416
+#define PCI_CHIP_HASWELL_M_ULT_GT2      0x0A16 /* Mobile ULT */
 
 #define IS_MOBILE(devid)	(devid == PCI_CHIP_I855_GM || \
 				 devid == PCI_CHIP_I915_GM || \
@@ -151,6 +158,24 @@
 				 devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \
 				 devid == PCI_CHIP_IVYBRIDGE_S)
 
+#define IS_GEN7(devid)          (IS_IVYBRIDGE(devid) || \
+                                 IS_HASWELL(devid))
+
+#define IS_IVYBRIDGE(dev)	(dev == PCI_CHIP_IVYBRIDGE_GT1 || \
+				 dev == PCI_CHIP_IVYBRIDGE_GT2 || \
+				 dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \
+				 dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \
+				 dev == PCI_CHIP_IVYBRIDGE_S || \
+				 dev == PCI_CHIP_IVYBRIDGE_S_GT2)
+
+#define IS_HSW_GT1(devid)       (devid == PCI_CHIP_HASWELL_GT1 || \
+                                 devid == PCI_CHIP_HASWELL_M_GT1)
+#define IS_HSW_GT2(devid)       (devid == PCI_CHIP_HASWELL_GT2 || \
+                                 devid == PCI_CHIP_HASWELL_M_GT2 || \
+                                 devid == PCI_CHIP_HASWELL_M_ULT_GT2)
+
+#define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
+                                 IS_HSW_GT2(devid))
 
 #define IS_965(devid)		(IS_GEN4(devid) || \
 				 IS_GEN5(devid) || \