From: York Sun <yorksun@freescale.com>
Date: Thu, 17 Mar 2011 18:18:12 +0000 (-0700)
Subject: powerpc/mpc8xxx: disable rcw_en bit for non-DDR3
X-Git-Tag: v2011.03-rc2~5
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4ca31929466b2804eac74d04ec7bf656c568250e;p=platform%2Fkernel%2Fu-boot.git

powerpc/mpc8xxx: disable rcw_en bit for non-DDR3

rcw_en bit is only available for DDR3 controllers. It is a reserved bit on
DDR1 and DDR2 controllers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 8ef6ca8..cefabe7 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -682,7 +682,9 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 		| ((obc_cfg & 0x1) << 6)
 		| ((ap_en & 0x1) << 5)
 		| ((d_init & 0x1) << 4)
+#ifdef CONFIG_FSL_DDR3
 		| ((rcw_en & 0x1) << 2)
+#endif
 		| ((md_en & 0x1) << 0)
 		);
 	debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);