From: Alexander Pivovarov Date: Fri, 3 Sep 2021 21:16:29 +0000 (-0700) Subject: [RISCV] Add SiFive cores E and S series X-Git-Tag: upstream/15.0.7~31911 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4bc8dbe0cae32f15008c1e98e7dd7d128e9dcbb6;p=platform%2Fupstream%2Fllvm.git [RISCV] Add SiFive cores E and S series Add SiFive cores E20, E21, E24, E34, S21, S54 and S76 Differential Revision: https://reviews.llvm.org/D109260 --- diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 6caf24c..56f91b4 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -73,7 +73,14 @@ Modified Compiler Flags - Support has been added for the following processors (``-mcpu`` identifiers in parentheses): + - RISC-V SiFive E20 (``sifive-e20``). + - RISC-V SiFive E21 (``sifive-e21``). + - RISC-V SiFive E24 (``sifive-e24``). + - RISC-V SiFive E34 (``sifive-e34``). + - RISC-V SiFive S21 (``sifive-s21``). - RISC-V SiFive S51 (``sifive-s51``). + - RISC-V SiFive S54 (``sifive-s54``). + - RISC-V SiFive S76 (``sifive-s76``). Removed Compiler Flags ------------------------- diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 4c26bf8..444b0ae 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -45,6 +45,39 @@ // RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s // MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64" +// mcpu with default march +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e20 | FileCheck -check-prefix=MCPU-SIFIVE-E20 %s +// MCPU-SIFIVE-E20: "-nostdsysteminc" "-target-cpu" "sifive-e20" +// MCPU-SIFIVE-E20: "-target-feature" "+m" "-target-feature" "+c" +// MCPU-SIFIVE-E20: "-target-abi" "ilp32" + +// mcpu with default march +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e21 | FileCheck -check-prefix=MCPU-SIFIVE-E21 %s +// MCPU-SIFIVE-E21: "-nostdsysteminc" "-target-cpu" "sifive-e21" +// MCPU-SIFIVE-E21: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+c" +// MCPU-SIFIVE-E21: "-target-abi" "ilp32" + +// mcpu with default march +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e24 | FileCheck -check-prefix=MCPU-SIFIVE-E24 %s +// MCPU-SIFIVE-E24: "-nostdsysteminc" "-target-cpu" "sifive-e24" +// MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" +// MCPU-SIFIVE-E24: "-target-feature" "+c" +// MCPU-SIFIVE-E24: "-target-abi" "ilp32" + +// mcpu with default march +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s +// MCPU-SIFIVE-E34: "-nostdsysteminc" "-target-cpu" "sifive-e34" +// MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" +// MCPU-SIFIVE-E34: "-target-feature" "+c" +// MCPU-SIFIVE-E34: "-target-abi" "ilp32" + +// mcpu with mabi option +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s +// MCPU-ABI-SIFIVE-S21: "-nostdsysteminc" "-target-cpu" "sifive-s21" +// MCPU-ABI-SIFIVE-S21: "-target-feature" "+m" "-target-feature" "+a" +// MCPU-ABI-SIFIVE-S21: "-target-feature" "+c" "-target-feature" "+64bit" +// MCPU-ABI-SIFIVE-S21: "-target-abi" "lp64" + // mcpu with mabi option // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s // MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51" @@ -53,6 +86,20 @@ // MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64" // mcpu with default march +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s54 | FileCheck -check-prefix=MCPU-SIFIVE-S54 %s +// MCPU-SIFIVE-S54: "-nostdsysteminc" "-target-cpu" "sifive-s54" +// MCPU-SIFIVE-S54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" +// MCPU-SIFIVE-S54: "-target-feature" "+c" "-target-feature" "+64bit" +// MCPU-SIFIVE-S54: "-target-abi" "lp64d" + +// mcpu with mabi option +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s76 | FileCheck -check-prefix=MCPU-SIFIVE-S76 %s +// MCPU-SIFIVE-S76: "-nostdsysteminc" "-target-cpu" "sifive-s76" +// MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" +// MCPU-SIFIVE-S76: "-target-feature" "+c" "-target-feature" "+64bit" +// MCPU-SIFIVE-S76: "-target-abi" "lp64d" + +// mcpu with default march // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s // MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54" // MCPU-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 4c3cd5e..aedad03 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -196,16 +196,16 @@ // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32 // RISCV32: error: unknown target CPU 'not-a-cpu' -// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e31, sifive-e76 +// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' -// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74 +// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e31, sifive-e76, generic, rocket, sifive-7-series +// TUNE-RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, generic, rocket, sifive-7-series // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74, generic, rocket, sifive-7-series +// TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, generic, rocket, sifive-7-series diff --git a/llvm/include/llvm/Support/RISCVTargetParser.def b/llvm/include/llvm/Support/RISCVTargetParser.def index 01f560a..f658cdb 100644 --- a/llvm/include/llvm/Support/RISCVTargetParser.def +++ b/llvm/include/llvm/Support/RISCVTargetParser.def @@ -19,10 +19,17 @@ PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""}) PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""}) PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""}) PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""}) +PROC(SIFIVE_E20, {"sifive-e20"}, FK_NONE, {"rv32imc"}) +PROC(SIFIVE_E21, {"sifive-e21"}, FK_NONE, {"rv32imac"}) +PROC(SIFIVE_E24, {"sifive-e24"}, FK_NONE, {"rv32imafc"}) PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"}) +PROC(SIFIVE_E34, {"sifive-e34"}, FK_NONE, {"rv32imafc"}) +PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"}) +PROC(SIFIVE_S21, {"sifive-s21"}, FK_64BIT, {"rv64imac"}) PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"}) +PROC(SIFIVE_S54, {"sifive-s54"}, FK_64BIT, {"rv64gc"}) +PROC(SIFIVE_S76, {"sifive-s76"}, FK_64BIT, {"rv64gc"}) PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"}) -PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"}) PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"}) #undef PROC diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 61034fd..284ff2f 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -250,27 +250,63 @@ def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>; def : ProcessorModel<"sifive-7-rv32", SiFive7Model, []>; def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit]>; +def : ProcessorModel<"sifive-e20", RocketModel, [FeatureStdExtM, + FeatureStdExtC]>; + +def : ProcessorModel<"sifive-e21", RocketModel, [FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtC]>; + +def : ProcessorModel<"sifive-e24", RocketModel, [FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtC]>; + def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM, FeatureStdExtA, FeatureStdExtC]>; +def : ProcessorModel<"sifive-e34", RocketModel, [FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtC]>; + +def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtC]>; + +def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtC]>; + def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit, FeatureStdExtM, FeatureStdExtA, FeatureStdExtC]>; -def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit, +def : ProcessorModel<"sifive-s54", RocketModel, [Feature64Bit, FeatureStdExtM, FeatureStdExtA, FeatureStdExtF, FeatureStdExtD, FeatureStdExtC]>; -def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM, +def : ProcessorModel<"sifive-s76", SiFive7Model, [Feature64Bit, + FeatureStdExtM, FeatureStdExtA, FeatureStdExtF, + FeatureStdExtD, FeatureStdExtC]>; +def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC]>; + def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit, FeatureStdExtM, FeatureStdExtA,