From: Jaehoon Chung Date: Mon, 9 Nov 2020 03:04:14 +0000 (+0900) Subject: mmc: meson_gx_mmc: change a clock phase to stable value X-Git-Tag: submit/tizen/20201110.005738~9 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4bb4f094318c97423c8a66c02e0eb6e69abba8cf;p=platform%2Fkernel%2Fu-boot.git mmc: meson_gx_mmc: change a clock phase to stable value Core clock phase value is changed from 180' to 270'. It's more stable than before. - Odroidn-N2/C4 : Working fine - VIM3 : Working fine Before this patch, Odroid-C4 doesn't work fine with 52MHz. Change-Id: Ica3b034a9c229b76e23cd3a5cb90fbf1f1350f34 Signed-off-by: Jaehoon Chung --- diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 719dd1e5e5..7c60e05665 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -52,10 +52,16 @@ static void meson_mmc_config_clock(struct mmc *mmc) } clk_div = DIV_ROUND_UP(clk, mmc->clock); - /* 180 phase core clock */ - meson_mmc_clk |= CLK_CO_PHASE_180; - - /* 180 phase tx clock */ + /* + * Clock Phase needs to set a proper value. + * It can be changed to other value. + * Because CORE : 270' Phase and TX : 0' Phase are stable, + * set to them by default. + */ + /* Core Clock Phase */ + meson_mmc_clk |= CLK_CO_PHASE_270; + + /* TX Clock Phase */ meson_mmc_clk |= CLK_TX_PHASE_000; /* clock settings */