From: Richard Sandiford Date: Mon, 19 Aug 2013 12:48:54 +0000 (+0000) Subject: [SystemZ] Add integer absolute (load positive) X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4b89705490ae9616b0ef0876595bf61cd3502b1e;p=platform%2Fupstream%2Fllvm.git [SystemZ] Add integer absolute (load positive) llvm-svn: 188670 --- diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td index 876b48b..dd3a9bc 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td @@ -534,11 +534,21 @@ let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1, } //===----------------------------------------------------------------------===// -// Negation +// Absolute and Negation //===----------------------------------------------------------------------===// let Defs = [CC] in { let CCValues = 0xF, CompareZeroCCMask = 0x8 in { + def LPR : UnaryRR <"lp", 0x10, z_iabs32, GR32, GR32>; + def LPGR : UnaryRRE<"lpg", 0xB900, z_iabs64, GR64, GR64>; + } + let CCValues = 0xE, CompareZeroCCMask = 0xE in + def LPGFR : UnaryRRE<"lpgf", 0xB910, null_frag, GR64, GR32>; +} +defm : SXU; + +let Defs = [CC] in { + let CCValues = 0xF, CompareZeroCCMask = 0x8 in { def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>; def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>; } diff --git a/llvm/lib/Target/SystemZ/SystemZOperators.td b/llvm/lib/Target/SystemZ/SystemZOperators.td index 8d6c619..59e1ffc 100644 --- a/llvm/lib/Target/SystemZ/SystemZOperators.td +++ b/llvm/lib/Target/SystemZ/SystemZOperators.td @@ -240,6 +240,14 @@ def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2), APInt::getLowBitsSet(BitWidth, 8)); }]>; +// Integer absolute, matching the canonical form generated by DAGCombiner. +def z_iabs32 : PatFrag<(ops node:$src), + (xor (add node:$src, (sra node:$src, (i32 31))), + (sra node:$src, (i32 31)))>; +def z_iabs64 : PatFrag<(ops node:$src), + (xor (add node:$src, (sra node:$src, (i32 63))), + (sra node:$src, (i32 63)))>; + // Fused multiply-add and multiply-subtract, but with the order of the // operands matching SystemZ's MA and MS instructions. def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3), diff --git a/llvm/test/CodeGen/SystemZ/int-abs-01.ll b/llvm/test/CodeGen/SystemZ/int-abs-01.ll new file mode 100644 index 0000000..40fb611 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/int-abs-01.ll @@ -0,0 +1,83 @@ +; Test integer absolute. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test i32->i32 absolute using slt. +define i32 @f1(i32 %val) { +; CHECK-LABEL: f1: +; CHECK: lpr %r2, %r2 +; CHECK: br %r14 + %cmp = icmp slt i32 %val, 0 + %neg = sub i32 0, %val + %res = select i1 %cmp, i32 %neg, i32 %val + ret i32 %res +} + +; Test i32->i32 absolute using sle. +define i32 @f2(i32 %val) { +; CHECK-LABEL: f2: +; CHECK: lpr %r2, %r2 +; CHECK: br %r14 + %cmp = icmp sle i32 %val, 0 + %neg = sub i32 0, %val + %res = select i1 %cmp, i32 %neg, i32 %val + ret i32 %res +} + +; Test i32->i32 absolute using sgt. +define i32 @f3(i32 %val) { +; CHECK-LABEL: f3: +; CHECK: lpr %r2, %r2 +; CHECK: br %r14 + %cmp = icmp sgt i32 %val, 0 + %neg = sub i32 0, %val + %res = select i1 %cmp, i32 %val, i32 %neg + ret i32 %res +} + +; Test i32->i32 absolute using sge. +define i32 @f4(i32 %val) { +; CHECK-LABEL: f4: +; CHECK: lpr %r2, %r2 +; CHECK: br %r14 + %cmp = icmp sge i32 %val, 0 + %neg = sub i32 0, %val + %res = select i1 %cmp, i32 %val, i32 %neg + ret i32 %res +} + +; Test i32->i64 absolute. +define i64 @f5(i32 %val) { +; CHECK-LABEL: f5: +; CHECK: lpgfr %r2, %r2 +; CHECK: br %r14 + %ext = sext i32 %val to i64 + %cmp = icmp slt i64 %ext, 0 + %neg = sub i64 0, %ext + %res = select i1 %cmp, i64 %neg, i64 %ext + ret i64 %res +} + +; Test i32->i64 absolute that uses an "in-register" form of sign extension. +define i64 @f6(i64 %val) { +; CHECK-LABEL: f6: +; CHECK: lpgfr %r2, %r2 +; CHECK: br %r14 + %trunc = trunc i64 %val to i32 + %ext = sext i32 %trunc to i64 + %cmp = icmp slt i64 %ext, 0 + %neg = sub i64 0, %ext + %res = select i1 %cmp, i64 %neg, i64 %ext + ret i64 %res +} + +; Test i64 absolute. +define i64 @f7(i64 %val) { +; CHECK-LABEL: f7: +; CHECK: lpgr %r2, %r2 +; CHECK: br %r14 + %cmp = icmp slt i64 %val, 0 + %neg = sub i64 0, %val + %res = select i1 %cmp, i64 %neg, i64 %val + ret i64 %res +} diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt index 328e2d6..9b31fd4 100644 --- a/llvm/test/MC/Disassembler/SystemZ/insns.txt +++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt @@ -3535,6 +3535,42 @@ # CHECK: lpebr %f15, %f9 0xb3 0x00 0x00 0xf9 +# CHECK: lpgfr %r0, %r0 +0xb9 0x10 0x00 0x00 + +# CHECK: lpgfr %r0, %r15 +0xb9 0x10 0x00 0x0f + +# CHECK: lpgfr %r15, %r0 +0xb9 0x10 0x00 0xf0 + +# CHECK: lpgfr %r7, %r8 +0xb9 0x10 0x00 0x78 + +# CHECK: lpgr %r0, %r0 +0xb9 0x00 0x00 0x00 + +# CHECK: lpgr %r0, %r15 +0xb9 0x00 0x00 0x0f + +# CHECK: lpgr %r15, %r0 +0xb9 0x00 0x00 0xf0 + +# CHECK: lpgr %r7, %r8 +0xb9 0x00 0x00 0x78 + +# CHECK: lpr %r0, %r0 +0x10 0x00 + +# CHECK: lpr %r0, %r15 +0x10 0x0f + +# CHECK: lpr %r15, %r0 +0x10 0xf0 + +# CHECK: lpr %r7, %r8 +0x10 0x78 + # CHECK: lpxbr %f0, %f8 0xb3 0x40 0x00 0x08 diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s index 52dc31d..47071f2 100644 --- a/llvm/test/MC/SystemZ/insn-good.s +++ b/llvm/test/MC/SystemZ/insn-good.s @@ -4757,6 +4757,36 @@ lpebr %f15,%f0 lpebr %f15,%f9 +#CHECK: lpgfr %r0, %r0 # encoding: [0xb9,0x10,0x00,0x00] +#CHECK: lpgfr %r0, %r15 # encoding: [0xb9,0x10,0x00,0x0f] +#CHECK: lpgfr %r15, %r0 # encoding: [0xb9,0x10,0x00,0xf0] +#CHECK: lpgfr %r7, %r8 # encoding: [0xb9,0x10,0x00,0x78] + + lpgfr %r0,%r0 + lpgfr %r0,%r15 + lpgfr %r15,%r0 + lpgfr %r7,%r8 + +#CHECK: lpgr %r0, %r0 # encoding: [0xb9,0x00,0x00,0x00] +#CHECK: lpgr %r0, %r15 # encoding: [0xb9,0x00,0x00,0x0f] +#CHECK: lpgr %r15, %r0 # encoding: [0xb9,0x00,0x00,0xf0] +#CHECK: lpgr %r7, %r8 # encoding: [0xb9,0x00,0x00,0x78] + + lpgr %r0,%r0 + lpgr %r0,%r15 + lpgr %r15,%r0 + lpgr %r7,%r8 + +#CHECK: lpr %r0, %r0 # encoding: [0x10,0x00] +#CHECK: lpr %r0, %r15 # encoding: [0x10,0x0f] +#CHECK: lpr %r15, %r0 # encoding: [0x10,0xf0] +#CHECK: lpr %r7, %r8 # encoding: [0x10,0x78] + + lpr %r0,%r0 + lpr %r0,%r15 + lpr %r15,%r0 + lpr %r7,%r8 + #CHECK: lpxbr %f0, %f8 # encoding: [0xb3,0x40,0x00,0x08] #CHECK: lpxbr %f0, %f13 # encoding: [0xb3,0x40,0x00,0x0d] #CHECK: lpxbr %f13, %f0 # encoding: [0xb3,0x40,0x00,0xd0]