From: Liu, Zhan <Zhan.Liu@amd.com>
Date: Thu, 2 Sep 2021 19:08:29 +0000 (-0400)
Subject: drm/amd/display: Fix DCN3 B0 DP Alt Mapping
X-Git-Tag: v6.1-rc5~2647^2~21^2~22
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4b7786d87fb3adf3e534c4f1e4f824d8700b786b;p=platform%2Fkernel%2Flinux-starfive.git

drm/amd/display: Fix DCN3 B0 DP Alt Mapping

[Why]
DCN3 B0 has a mux, which redirects PHYC and PHYD to PHYF and PHYG.

[How]
Fix DIG mapping.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Zhan Liu <Zhan.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 613d34b..a823a64 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1383,6 +1383,12 @@ static struct stream_encoder *dcn31_stream_encoder_create(
 		return NULL;
 	}
 
+	if (ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
+			ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
+		if ((eng_id == ENGINE_ID_DIGC) || (eng_id == ENGINE_ID_DIGD))
+			eng_id = eng_id + 3; // For B0 only. C->F, D->G.
+	}
+
 	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
 					eng_id, vpg, afmt,
 					&stream_enc_regs[eng_id],