From: Bjorn Andersson Date: Tue, 26 Feb 2019 07:02:21 +0000 (-0800) Subject: clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks X-Git-Tag: v5.4-rc1~1399^2~6^4 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4b5a59a265f05a41df6bb3449d8c6db50577dca5;p=platform%2Fkernel%2Flinux-rpi.git clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks The PCIe PIPE clock in the GCC is fed by the PIPE clock coming from the PHY, describe this relationship. Signed-off-by: Bjorn Andersson Signed-off-by: Stephen Boyd --- diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index c782e62..838438961 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -1697,6 +1697,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk", + .parent_names = (const char *[]){ "pcie_0_pipe_clk" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1796,6 +1799,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = { .enable_mask = BIT(30), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk", + .parent_names = (const char *[]){ "pcie_1_pipe_clk" }, + .num_parents = 1, .ops = &clk_branch2_ops, }, },