From: Florian Fainelli <f.fainelli@gmail.com>
Date: Wed, 22 Nov 2017 01:37:46 +0000 (-0800)
Subject: net: dsa: bcm_sf2: Clear IDDQ_GLOBAL_PWR bit for PHY
X-Git-Tag: v4.19~2099^2~4
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4b52d010113e11006a389f2a8315167ede9e0b10;p=platform%2Fkernel%2Flinux-rpi.git

net: dsa: bcm_sf2: Clear IDDQ_GLOBAL_PWR bit for PHY

The PHY on BCM7278 has an additional bit that needs to be cleared:
IDDQ_GLOBAL_PWR, without doing this, the PHY remains stuck in reset out
of suspend/resume cycles.

Fixes: 0fe9933804eb ("net: dsa: bcm_sf2: Add support for BCM7278 integrated switch")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---

diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
index 93faa1fe..ea01f24 100644
--- a/drivers/net/dsa/bcm_sf2.c
+++ b/drivers/net/dsa/bcm_sf2.c
@@ -95,7 +95,7 @@ static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
 	reg = reg_readl(priv, REG_SPHY_CNTRL);
 	if (enable) {
 		reg |= PHY_RESET;
-		reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
+		reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
 		reg_writel(priv, reg, REG_SPHY_CNTRL);
 		udelay(21);
 		reg = reg_readl(priv, REG_SPHY_CNTRL);