From: Tom Musta <tommusta@gmail.com>
Date: Thu, 29 May 2014 14:12:24 +0000 (-0500)
Subject: target-ppc: Store Quadword Conditional Drops Size Bit
X-Git-Tag: TizenStudio_2.0_p2.3.2~208^2~773^2~45
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4b1daa72d3b68b050bb9013edd0888972a0e22dd;p=sdk%2Femulator%2Fqemu.git

target-ppc: Store Quadword Conditional Drops Size Bit

The size and register information are encoded into the reserve_info field
of CPU state in the store conditional translation code.  Specifically, the
size is shifted left by 5 bits (see target-ppc/translate.c gen_conditional_store).

The user-mode store conditional code erroneously extracts the size by ANDing
with a 4 bit mask; this breaks if size >= 16.

Eliminate the mask to make the extraction of size mirror its encoding.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---

diff --git a/linux-user/main.c b/linux-user/main.c
index f577e19..a87c6f7 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -1497,7 +1497,7 @@ static int do_store_exclusive(CPUPPCState *env)
         segv = 1;
     } else {
         int reg = env->reserve_info & 0x1f;
-        int size = (env->reserve_info >> 5) & 0xf;
+        int size = env->reserve_info >> 5;
         int stored = 0;
 
         if (addr == env->reserve_addr) {