From: Simon Horman Date: Mon, 25 Mar 2019 16:35:56 +0000 (+0100) Subject: clk: renesas: r8a774c0: Add Z2 clock X-Git-Tag: v5.4-rc1~946^2~7^2~1^2~7 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4aeed945b7024e454bafb4beb68b8c0298832efb;p=platform%2Fkernel%2Flinux-rpi.git clk: renesas: r8a774c0: Add Z2 clock Adds support for RZ/G2E (r8a774c0) Z2 clock. Signed-off-by: Simon Horman Tested-by: Fabrizio Castro Reviewed-by: Fabrizio Castro Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index 34e274f..57098b7 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1), DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1), + DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8), DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1), DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1),