From: Kunal Pathak <Kunal.Pathak@microsoft.com>
Date: Thu, 10 Aug 2023 11:05:46 +0000 (-0700)
Subject: Lsra JitStressRegs mode SpillAlways fixes (#89720)
X-Git-Tag: accepted/tizen/unified/riscv/20231226.055536~390
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4aea2aa559a66432cd22e07e028f38bff50c7889;p=platform%2Fupstream%2Fdotnet%2Fruntime.git

Lsra JitStressRegs mode SpillAlways fixes (#89720)

* fix few scenarios for spillAlways()

* Include JitStressRegs=0x800

* Revert "Include JitStressRegs=0x800"

This reverts commit 170233235b3e24530386f48569a3e6f9d1de2b70.
---

diff --git a/src/coreclr/jit/lsra.cpp b/src/coreclr/jit/lsra.cpp
index aa85b85..5c8fe4a 100644
--- a/src/coreclr/jit/lsra.cpp
+++ b/src/coreclr/jit/lsra.cpp
@@ -4871,6 +4871,7 @@ void LinearScan::allocateRegisters()
 
         if (spillAlways() && lastAllocatedRefPosition != nullptr && !lastAllocatedRefPosition->IsPhysRegRef() &&
             !lastAllocatedRefPosition->getInterval()->isInternal &&
+            (!lastAllocatedRefPosition->RegOptional() || (lastAllocatedRefPosition->registerAssignment != RBM_NONE)) &&
             (RefTypeIsDef(lastAllocatedRefPosition->refType) || lastAllocatedRefPosition->getInterval()->isLocalVar))
         {
             assert(lastAllocatedRefPosition->registerAssignment != RBM_NONE);
@@ -5015,7 +5016,7 @@ void LinearScan::allocateRegisters()
                     {
                         // Available registers should not hold constants
                         assert(isRegAvailable(reg, physRegRecord->registerType));
-                        assert(!isRegConstant(reg, physRegRecord->registerType));
+                        assert(!isRegConstant(reg, physRegRecord->registerType) || spillAlways());
                         assert(nextIntervalRef[reg] == MaxLocation);
                         assert(spillCost[reg] == 0);
                     }