From: Palmer Dabbelt Date: Thu, 9 Mar 2023 23:46:40 +0000 (-0800) Subject: Merge patch series "riscv, mm: detect svnapot cpu support at runtime" X-Git-Tag: v6.6.7~2955^2~20 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4a4c459872f154acf872dfa6baf5d1edabd52323;p=platform%2Fkernel%2Flinux-starfive.git Merge patch series "riscv, mm: detect svnapot cpu support at runtime" Qinglin Pan says: Svnapot is a RISC-V extension for marking contiguous 4K pages as a non-4K page. This patch set is for using Svnapot in hugetlb fs and huge vmap. This patchset adds a Kconfig item for using Svnapot in "Platform type"->"SVNAPOT extension support". Its default value is on, and people can set it off if they don't allow kernel to detect Svnapot hardware support and leverage it. Tested on: - qemu rv64 with "Svnapot support" off and svnapot=true. - qemu rv64 with "Svnapot support" on and svnapot=true. - qemu rv64 with "Svnapot support" off and svnapot=false. - qemu rv64 with "Svnapot support" on and svnapot=false. * b4-shazam-merge: riscv: mm: support Svnapot in huge vmap riscv: mm: support Svnapot in hugetlb page riscv: mm: modify pte format for Svnapot Link: https://lore.kernel.org/r/20230209131647.17245-1-panqinglin00@gmail.com [Palmer: fix up the feature ordering in the merge] Signed-off-by: Palmer Dabbelt --- 4a4c459872f154acf872dfa6baf5d1edabd52323 diff --cc arch/riscv/Kconfig index c5e42cc,a81a891..c736dc8 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@@ -44,10 -44,8 +44,10 @@@ config RISC select ARCH_USE_QUEUED_RWLOCKS select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU select ARCH_WANT_FRAME_POINTERS - select ARCH_WANT_GENERAL_HUGETLB + select ARCH_WANT_GENERAL_HUGETLB if !RISCV_ISA_SVNAPOT + select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP select ARCH_WANT_HUGE_PMD_SHARE if 64BIT + select ARCH_WANT_LD_ORPHAN_WARN if !XIP_KERNEL select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU select BUILDTIME_TABLE_SORT if MMU diff --cc arch/riscv/include/asm/hwcap.h index e3021b2,6e368d3..0ed15c2a --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@@ -24,27 -24,30 +24,28 @@@ #define RISCV_ISA_EXT_u ('u' - 'a') /* - * Increse this to higher value as kernel support more ISA extensions. + * These macros represent the logical IDs of each multi-letter RISC-V ISA + * extension and are used in the ISA bitmap. The logical IDs start from + * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single + * letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order + * to allocate the bitmap and may be increased when necessary. + * + * New extensions should just be added to the bottom, rather than added + * alphabetically, in order to avoid unnecessary shuffling. */ -#define RISCV_ISA_EXT_MAX 64 -#define RISCV_ISA_EXT_NAME_LEN_MAX 32 +#define RISCV_ISA_EXT_BASE 26 -/* The base ID for multi-letter ISA extensions */ -#define RISCV_ISA_EXT_BASE 26 +#define RISCV_ISA_EXT_SSCOFPMF 26 +#define RISCV_ISA_EXT_SSTC 27 +#define RISCV_ISA_EXT_SVINVAL 28 +#define RISCV_ISA_EXT_SVPBMT 29 +#define RISCV_ISA_EXT_ZBB 30 +#define RISCV_ISA_EXT_ZICBOM 31 +#define RISCV_ISA_EXT_ZIHINTPAUSE 32 ++#define RISCV_ISA_EXT_SVNAPOT 33 -/* - * These macros represent the logical ID for each multi-letter RISC-V ISA extension. - * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed - * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter - * extensions while all the multi-letter extensions should define the next - * available logical extension id. - * Entries are sorted alphabetically. - */ -#define RISCV_ISA_EXT_SSCOFPMF 26 -#define RISCV_ISA_EXT_SSTC 27 -#define RISCV_ISA_EXT_SVINVAL 28 -#define RISCV_ISA_EXT_SVNAPOT 29 -#define RISCV_ISA_EXT_SVPBMT 30 -#define RISCV_ISA_EXT_ZBB 31 -#define RISCV_ISA_EXT_ZICBOM 32 -#define RISCV_ISA_EXT_ZIHINTPAUSE 33 +#define RISCV_ISA_EXT_MAX 64 +#define RISCV_ISA_EXT_NAME_LEN_MAX 32 #ifndef __ASSEMBLY__