From: Xingyu Wu <xingyu.wu@starfivetech.com>
Date: Thu, 3 Nov 2022 02:37:08 +0000 (+0800)
Subject: riscv: dts: starfive: jh7110: Add watchdog node
X-Git-Tag: accepted/tizen/unified/riscv/20230718.024919~193
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4a46f0e442bad0a71702e271857d11154bf61d57;p=platform%2Fkernel%2Flinux-starfive.git

riscv: dts: starfive: jh7110: Add watchdog node

Add the watchdog node for the Starfive JH7110 SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 7e0de0ab5962..3190bcb0ab21 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -530,6 +530,16 @@
 			#gpio-cells = <2>;
 		};
 
+		wdog: watchdog@13070000 {
+			compatible = "starfive,jh7110-wdt";
+			reg = <0x0 0x13070000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
+				 <&syscrg JH7110_SYSCLK_WDT_CORE>;
+			clock-names = "apb", "core";
+			resets = <&syscrg JH7110_SYSRST_WDT_APB>,
+				 <&syscrg JH7110_SYSRST_WDT_CORE>;
+		};
+
 		aoncrg: clock-controller@17000000 {
 			compatible = "starfive,jh7110-aoncrg";
 			reg = <0x0 0x17000000 0x0 0x10000>;