From: Xiaojie Yuan Date: Thu, 16 May 2019 10:05:37 +0000 (+0800) Subject: drm/amdgpu/gmc10: set gart size and vm size for navi12 X-Git-Tag: v5.4-rc1~32^2~19^2~36 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=4a0e815fb3180875f8763321e5d2e2b432d35f1a;p=platform%2Fkernel%2Flinux-rpi.git drm/amdgpu/gmc10: set gart size and vm size for navi12 Same as other navi asics. Signed-off-by: Xiaojie Yuan Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 0fd85cb1..f585fc9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -525,6 +525,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_NAVI10: case CHIP_NAVI14: + case CHIP_NAVI12: default: adev->gmc.gart_size = 512ULL << 20; break; @@ -603,10 +604,11 @@ static int gmc_v10_0_sw_init(void *handle) switch (adev->asic_type) { case CHIP_NAVI10: case CHIP_NAVI14: + case CHIP_NAVI12: adev->num_vmhubs = 2; /* * To fulfill 4-level page support, - * vm size is 256TB (48bit), maximum size of Navi10/Navi14, + * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, * block size 512 (9bit) */ amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); @@ -721,6 +723,7 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_NAVI10: case CHIP_NAVI14: + case CHIP_NAVI12: break; default: break;