From: Marek Olšák Date: Fri, 11 Nov 2016 20:14:03 +0000 (+0100) Subject: gallium/radeon: add RADEON_SURF_OPTIMIZE_FOR_SPACE X-Git-Tag: upstream/17.1.0~4500 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=49fa4a4e600cbb35c43a85fab2ed4aac3e6acccf;p=platform%2Fupstream%2Fmesa.git gallium/radeon: add RADEON_SURF_OPTIMIZE_FOR_SPACE FORCE_TILING should disable it. It has no effect now, but that may change soon. Tested-by: Edmondo Tommasina Reviewed-by: Nicolai Hähnle --- diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 97673ee..259ff36 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -253,6 +253,8 @@ static int r600_init_surface(struct r600_common_screen *rscreen, if (is_imported) flags |= RADEON_SURF_IMPORTED; + if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING)) + flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE; r = rscreen->ws->surface_init(rscreen->ws, ptex, flags, bpe, array_mode, surface); diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index 3e30e95..3027c4a 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -281,6 +281,7 @@ enum radeon_micro_mode { #define RADEON_SURF_DISABLE_DCC (1 << 22) #define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23) #define RADEON_SURF_IMPORTED (1 << 24) +#define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25) struct radeon_surf_level { uint64_t offset; diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index d65dae7..d8ab28b 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -402,7 +402,9 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, * requested, because TC-compatible HTILE requires 2D tiling. */ AddrSurfInfoIn.flags.degrade4Space = !AddrSurfInfoIn.flags.tcCompatible && - !(flags & RADEON_SURF_FMASK); + !AddrSurfInfoIn.flags.fmask && + tex->nr_samples <= 1 && + (flags & RADEON_SURF_OPTIMIZE_FOR_SPACE); /* DCC notes: * - If we add MSAA support, keep in mind that CB can't decompress 8bpp