From: Andrea Corallo <andrea.corallo@arm.com>
Date: Wed, 9 Dec 2020 16:59:12 +0000 (+0100)
Subject: ira.c: Fix ICE in ira-color [PR97092]
X-Git-Tag: upstream/12.2.0~11028
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=499651e43854ea65303eb55324263c25256c9735;p=platform%2Fupstream%2Fgcc.git

ira.c: Fix ICE in ira-color [PR97092]

gcc/ChangeLog

2020-12-10  Andrea Corallo  <andrea.corallo@arm.com>

	PR rtl-optimization/97092
	* ira-color.c (update_costs_from_allocno): Do not carry over mode
	between subsequent iterations.

gcc/testsuite/ChangeLog

2020-12-10  Andrea Corallo  <andrea.corallo@arm.com>

	* gcc.target/aarch64/sve/pr97092.c: New test.
---

diff --git a/gcc/ira-color.c b/gcc/ira-color.c
index d3f8e23..eb52539 100644
--- a/gcc/ira-color.c
+++ b/gcc/ira-color.c
@@ -1407,9 +1407,11 @@ update_costs_from_allocno (ira_allocno_t allocno, int hard_regno,
 	     register classes bigger modes might be invalid,
 	     e.g. DImode for AREG on x86.  For such cases the
 	     register move cost will be maximal.  */
-	  mode = narrower_subreg_mode (mode, ALLOCNO_MODE (cp->second));
+	  mode = narrower_subreg_mode (ALLOCNO_MODE (cp->first),
+				       ALLOCNO_MODE (cp->second));
+
 	  ira_init_register_move_cost_if_necessary (mode);
-	  
+
 	  cost = (cp->second == allocno
 		  ? ira_register_move_cost[mode][rclass][aclass]
 		  : ira_register_move_cost[mode][aclass][rclass]);
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr97092.c b/gcc/testsuite/gcc.target/aarch64/sve/pr97092.c
new file mode 100644
index 0000000..69f7a3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr97092.c
@@ -0,0 +1,24 @@
+/* { dg-do assemble { target aarch64_asm_sve_ok } } */
+/* { dg-options "-O1 -ftree-vectorize -march=armv8.2-a+sve" } */
+
+void g (void);
+long a;
+
+signed char
+bar (int c, int d)
+{
+  return c + d;
+}
+
+void
+foo (void)
+{
+  int f;
+  for (; (long)foo < 4;) {
+    f = 0;
+    for (; f < 10; f++);
+    g ();
+    a = -4;
+    for (; a; a = bar (a, 1));
+  }
+}