From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Fri, 14 Oct 2022 18:21:11 +0000 (-0700)
Subject: Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel... 
X-Git-Tag: v6.6.17~6358
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=498574970fc968ee17cfea9e6959b78c094c00a5;p=platform%2Fkernel%2Flinux-rpi.git

Merge tag 'riscv-for-linus-6.1-mw2' of git://git./linux/kernel/git/riscv/linux

Pull more RISC-V updates from Palmer Dabbelt:

 - DT updates for the PolarFire SOC

 - a fix to correct the handling of write-only mappings

 - m{vetndor,arcd,imp}id is now in /proc/cpuinfo

 - the SiFive L2 cache controller support has been refactored to also
   support L3 caches

 - misc fixes, cleanups and improvements throughout the tree

* tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits)
  MAINTAINERS: add RISC-V's patchwork
  RISC-V: Make port I/O string accessors actually work
  riscv: enable software resend of irqs
  RISC-V: Re-enable counter access from userspace
  riscv: vdso: fix NULL deference in vdso_join_timens() when vfork
  riscv: Add cache information in AUX vector
  soc: sifive: ccache: define the macro for the register shifts
  soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes
  soc: sifive: ccache: reduce printing on init
  soc: sifive: ccache: determine the cache level from dts
  soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.
  dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache
  riscv: check for kernel config option in t-head memory types errata
  riscv: use BIT() marco for cpufeature probing
  riscv: use BIT() macros in t-head errata init
  riscv: drop some idefs from CMO initialization
  riscv: cleanup svpbmt cpufeature probing
  riscv: Pass -mno-relax only on lld < 15.0.0
  RISC-V: Avoid dereferening NULL regs in die()
  dt-bindings: riscv: add new riscv,isa strings for emulators
  ...
---

498574970fc968ee17cfea9e6959b78c094c00a5
diff --cc Documentation/devicetree/bindings/riscv/microchip.yaml
index 37f97ee,614f252..714d0fc
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@@ -4,11 -4,11 +4,11 @@@
  $id: http://devicetree.org/schemas/riscv/microchip.yaml#
  $schema: http://devicetree.org/meta-schemas/core.yaml#
  
 -title: Microchip PolarFire SoC-based boards device tree bindings
 +title: Microchip PolarFire SoC-based boards
  
  maintainers:
-   - Cyril Jean <Cyril.Jean@microchip.com>
-   - Lewis Hanly <lewis.hanly@microchip.com>
+   - Conor Dooley <conor.dooley@microchip.com>
+   - Daire McNamara <daire.mcnamara@microchip.com>
  
  description:
    Microchip PolarFire SoC-based boards
diff --cc arch/riscv/kernel/vdso.c
index 692e7ae3,4abc9ae..123d052
--- a/arch/riscv/kernel/vdso.c
+++ b/arch/riscv/kernel/vdso.c
@@@ -114,16 -119,18 +119,19 @@@ int vdso_join_timens(struct task_struc
  {
  	struct mm_struct *mm = task->mm;
  	struct vm_area_struct *vma;
 +	VMA_ITERATOR(vmi, mm, 0);
- 	struct __vdso_info *vdso_info = mm->context.vdso_info;
  
  	mmap_read_lock(mm);
  
 -	for (vma = mm->mmap; vma; vma = vma->vm_next) {
 +	for_each_vma(vmi, vma) {
  		unsigned long size = vma->vm_end - vma->vm_start;
  
- 		if (vma_is_special_mapping(vma, vdso_info->dm))
+ 		if (vma_is_special_mapping(vma, vdso_info.dm))
  			zap_page_range(vma, vma->vm_start, size);
+ #ifdef CONFIG_COMPAT
+ 		if (vma_is_special_mapping(vma, compat_vdso_info.dm))
+ 			zap_page_range(vma, vma->vm_start, size);
+ #endif
  	}
  
  	mmap_read_unlock(mm);