From: Samuel Pitoiset Date: Mon, 28 Aug 2023 13:10:28 +0000 (+0200) Subject: radv: re-order IO slot layout for stages that aren't linked X-Git-Tag: upstream/23.3.3~2703 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=496a17bffeacd8172e9a3306ddcf4b919f196b79;p=platform%2Fupstream%2Fmesa.git radv: re-order IO slot layout for stages that aren't linked Otherwise, if eg. PSIZ is exported the ESGS stride is wrong. This isn't optimal yet but let's start with this to support separate compilation of VS/TCS/TES/GS correctly first. This fixes a bunch of issues when forcing separate compilation on RDNA2. Signed-off-by: Samuel Pitoiset Part-of: --- diff --git a/src/amd/vulkan/nir/radv_nir_lower_io.c b/src/amd/vulkan/nir/radv_nir_lower_io.c index 049d042..0b98bcd 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_io.c +++ b/src/amd/vulkan/nir/radv_nir_lower_io.c @@ -105,10 +105,10 @@ radv_nir_lower_io(struct radv_device *device, nir_shader *nir) /* IO slot layout for stages that aren't linked. */ enum { RADV_IO_SLOT_POS = 0, - RADV_IO_SLOT_VAR0 = 1, /* 0..31 */ - RADV_IO_SLOT_CLIP_DIST0 = 33, + RADV_IO_SLOT_CLIP_DIST0, RADV_IO_SLOT_CLIP_DIST1, RADV_IO_SLOT_PSIZ, + RADV_IO_SLOT_VAR0, /* 0..31 */ }; static unsigned