From: Fraser Cormack Date: Wed, 5 May 2021 12:01:04 +0000 (+0100) Subject: [RISCV][VP][NFC] Add tests for VP_SHL and VP_LSHR X-Git-Tag: llvmorg-14-init~7572 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=491a3d135993d22589c1a154217fdb24510d35d1;p=platform%2Fupstream%2Fllvm.git [RISCV][VP][NFC] Add tests for VP_SHL and VP_LSHR As agreed in D101826, these are follow-up tests for the RISC-V VP support. Tests for VP_ASHR were landed as part of D101826. --- diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll new file mode 100644 index 0000000..5c1478a --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll @@ -0,0 +1,1333 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 + +declare <2 x i8> @llvm.vp.shl.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32) + +define <2 x i8> @vsll_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + ret <2 x i8> %v +} + +define <2 x i8> @vsll_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v2i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + ret <2 x i8> %v +} + +define <2 x i8> @vsll_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer + %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i8> %v +} + +define <2 x i8> @vsll_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v2i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i8> %v +} + +define <2 x i8> @vsll_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i8> undef, i8 3, i32 0 + %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer + %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i8> %v +} + +define <2 x i8> @vsll_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v2i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i8> undef, i8 3, i32 0 + %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i8> %v +} + +declare <4 x i8> @llvm.vp.shl.v4i8(<4 x i8>, <4 x i8>, <4 x i1>, i32) + +define <4 x i8> @vsll_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v4i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + ret <4 x i8> %v +} + +define <4 x i8> @vsll_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v4i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + ret <4 x i8> %v +} + +define <4 x i8> @vsll_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v4i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer + %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i8> %v +} + +define <4 x i8> @vsll_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v4i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i8> %v +} + +define <4 x i8> @vsll_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v4i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i8> undef, i8 3, i32 0 + %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer + %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i8> %v +} + +define <4 x i8> @vsll_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v4i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i8> undef, i8 3, i32 0 + %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i8> %v +} + +declare <8 x i8> @llvm.vp.shl.v8i8(<8 x i8>, <8 x i8>, <8 x i1>, i32) + +define <8 x i8> @vsll_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + ret <8 x i8> %v +} + +define <8 x i8> @vsll_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v8i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + ret <8 x i8> %v +} + +define <8 x i8> @vsll_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer + %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i8> %v +} + +define <8 x i8> @vsll_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v8i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i8> %v +} + +define <8 x i8> @vsll_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i8> undef, i8 3, i32 0 + %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer + %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i8> %v +} + +define <8 x i8> @vsll_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v8i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i8> undef, i8 3, i32 0 + %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i8> %v +} + +declare <16 x i8> @llvm.vp.shl.v16i8(<16 x i8>, <16 x i8>, <16 x i1>, i32) + +define <16 x i8> @vsll_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v16i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + ret <16 x i8> %v +} + +define <16 x i8> @vsll_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v16i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + ret <16 x i8> %v +} + +define <16 x i8> @vsll_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v16i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer + %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i8> %v +} + +define <16 x i8> @vsll_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v16i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i8> %v +} + +define <16 x i8> @vsll_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v16i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i8> undef, i8 3, i32 0 + %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer + %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i8> %v +} + +define <16 x i8> @vsll_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v16i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i8> undef, i8 3, i32 0 + %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i8> %v +} + +declare <2 x i16> @llvm.vp.shl.v2i16(<2 x i16>, <2 x i16>, <2 x i1>, i32) + +define <2 x i16> @vsll_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + ret <2 x i16> %v +} + +define <2 x i16> @vsll_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v2i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + ret <2 x i16> %v +} + +define <2 x i16> @vsll_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer + %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i16> %v +} + +define <2 x i16> @vsll_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v2i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i16> %v +} + +define <2 x i16> @vsll_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i16> undef, i16 3, i32 0 + %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer + %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i16> %v +} + +define <2 x i16> @vsll_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v2i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i16> undef, i16 3, i32 0 + %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i16> %v +} + +declare <4 x i16> @llvm.vp.shl.v4i16(<4 x i16>, <4 x i16>, <4 x i1>, i32) + +define <4 x i16> @vsll_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v4i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + ret <4 x i16> %v +} + +define <4 x i16> @vsll_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v4i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + ret <4 x i16> %v +} + +define <4 x i16> @vsll_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v4i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer + %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i16> %v +} + +define <4 x i16> @vsll_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v4i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i16> %v +} + +define <4 x i16> @vsll_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v4i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i16> undef, i16 3, i32 0 + %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer + %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i16> %v +} + +define <4 x i16> @vsll_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v4i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i16> undef, i16 3, i32 0 + %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i16> %v +} + +declare <8 x i16> @llvm.vp.shl.v8i16(<8 x i16>, <8 x i16>, <8 x i1>, i32) + +define <8 x i16> @vsll_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + ret <8 x i16> %v +} + +define <8 x i16> @vsll_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v8i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + ret <8 x i16> %v +} + +define <8 x i16> @vsll_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer + %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i16> %v +} + +define <8 x i16> @vsll_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v8i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i16> %v +} + +define <8 x i16> @vsll_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i16> undef, i16 3, i32 0 + %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer + %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i16> %v +} + +define <8 x i16> @vsll_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v8i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i16> undef, i16 3, i32 0 + %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i16> %v +} + +declare <16 x i16> @llvm.vp.shl.v16i16(<16 x i16>, <16 x i16>, <16 x i1>, i32) + +define <16 x i16> @vsll_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t +; CHECK-NEXT: ret + %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + ret <16 x i16> %v +} + +define <16 x i16> @vsll_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v16i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10 +; CHECK-NEXT: ret + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + ret <16 x i16> %v +} + +define <16 x i16> @vsll_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer + %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i16> %v +} + +define <16 x i16> @vsll_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v16i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i16> %v +} + +define <16 x i16> @vsll_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i16> undef, i16 3, i32 0 + %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer + %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i16> %v +} + +define <16 x i16> @vsll_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v16i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i16> undef, i16 3, i32 0 + %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i16> %v +} + +declare <2 x i32> @llvm.vp.shl.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32) + +define <2 x i32> @vsll_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v2i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + ret <2 x i32> %v +} + +define <2 x i32> @vsll_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v2i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + ret <2 x i32> %v +} + +define <2 x i32> @vsll_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v2i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer + %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i32> %v +} + +define <2 x i32> @vsll_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v2i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i32> %v +} + +define <2 x i32> @vsll_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v2i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i32> undef, i32 3, i32 0 + %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer + %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i32> %v +} + +define <2 x i32> @vsll_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v2i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i32> undef, i32 3, i32 0 + %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i32> %v +} + +declare <4 x i32> @llvm.vp.shl.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32) + +define <4 x i32> @vsll_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + ret <4 x i32> %v +} + +define <4 x i32> @vsll_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v4i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + ret <4 x i32> %v +} + +define <4 x i32> @vsll_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer + %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i32> %v +} + +define <4 x i32> @vsll_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v4i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i32> %v +} + +define <4 x i32> @vsll_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i32> undef, i32 3, i32 0 + %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer + %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i32> %v +} + +define <4 x i32> @vsll_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v4i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i32> undef, i32 3, i32 0 + %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i32> %v +} + +declare <8 x i32> @llvm.vp.shl.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) + +define <8 x i32> @vsll_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t +; CHECK-NEXT: ret + %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + ret <8 x i32> %v +} + +define <8 x i32> @vsll_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v8i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10 +; CHECK-NEXT: ret + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + ret <8 x i32> %v +} + +define <8 x i32> @vsll_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer + %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i32> %v +} + +define <8 x i32> @vsll_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v8i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i32> %v +} + +define <8 x i32> @vsll_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i32> undef, i32 3, i32 0 + %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer + %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i32> %v +} + +define <8 x i32> @vsll_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v8i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i32> undef, i32 3, i32 0 + %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i32> %v +} + +declare <16 x i32> @llvm.vp.shl.v16i32(<16 x i32>, <16 x i32>, <16 x i1>, i32) + +define <16 x i32> @vsll_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v16i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t +; CHECK-NEXT: ret + %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + ret <16 x i32> %v +} + +define <16 x i32> @vsll_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v16i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12 +; CHECK-NEXT: ret + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + ret <16 x i32> %v +} + +define <16 x i32> @vsll_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v16i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer + %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i32> %v +} + +define <16 x i32> @vsll_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_v16i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i32> %v +} + +define <16 x i32> @vsll_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v16i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i32> undef, i32 3, i32 0 + %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer + %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i32> %v +} + +define <16 x i32> @vsll_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v16i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i32> undef, i32 3, i32 0 + %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i32> %v +} + +declare <2 x i64> @llvm.vp.shl.v2i64(<2 x i64>, <2 x i64>, <2 x i1>, i32) + +define <2 x i64> @vsll_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v2i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + ret <2 x i64> %v +} + +define <2 x i64> @vsll_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v2i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + ret <2 x i64> %v +} + +define <2 x i64> @vsll_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_v2i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 2, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m1,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v25, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_v2i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement <2 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer + %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i64> %v +} + +define <2 x i64> @vsll_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_v2i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 2, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m1,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v25 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_v2i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement <2 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i64> %v +} + +define <2 x i64> @vsll_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v2i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i64> undef, i64 3, i32 0 + %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer + %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i64> %v +} + +define <2 x i64> @vsll_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v2i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i64> undef, i64 3, i32 0 + %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i64> %v +} + +declare <4 x i64> @llvm.vp.shl.v4i64(<4 x i64>, <4 x i64>, <4 x i1>, i32) + +define <4 x i64> @vsll_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v4i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t +; CHECK-NEXT: ret + %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + ret <4 x i64> %v +} + +define <4 x i64> @vsll_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v4i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10 +; CHECK-NEXT: ret + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + ret <4 x i64> %v +} + +define <4 x i64> @vsll_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_v4i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 4, e64,m2,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m2,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v26, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_v4i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement <4 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer + %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i64> %v +} + +define <4 x i64> @vsll_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_v4i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 4, e64,m2,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m2,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v26 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_v4i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement <4 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i64> %v +} + +define <4 x i64> @vsll_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v4i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i64> undef, i64 3, i32 0 + %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer + %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i64> %v +} + +define <4 x i64> @vsll_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v4i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i64> undef, i64 3, i32 0 + %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i64> %v +} + +declare <8 x i64> @llvm.vp.shl.v8i64(<8 x i64>, <8 x i64>, <8 x i1>, i32) + +define <8 x i64> @vsll_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v8i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t +; CHECK-NEXT: ret + %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + ret <8 x i64> %v +} + +define <8 x i64> @vsll_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v8i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12 +; CHECK-NEXT: ret + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + ret <8 x i64> %v +} + +define <8 x i64> @vsll_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 8, e64,m4,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m4,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v28, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement <8 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer + %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i64> %v +} + +define <8 x i64> @vsll_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_v8i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 8, e64,m4,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m4,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v28 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_v8i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement <8 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i64> %v +} + +define <8 x i64> @vsll_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v8i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i64> undef, i64 3, i32 0 + %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer + %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i64> %v +} + +define <8 x i64> @vsll_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v8i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i64> undef, i64 3, i32 0 + %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i64> %v +} + +declare <16 x i64> @llvm.vp.shl.v16i64(<16 x i64>, <16 x i64>, <16 x i1>, i32) + +define <16 x i64> @vsll_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v16i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t +; CHECK-NEXT: ret + %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + ret <16 x i64> %v +} + +define <16 x i64> @vsll_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_v16i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16 +; CHECK-NEXT: ret + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + ret <16 x i64> %v +} + +define <16 x i64> @vsll_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_v16i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 16, e64,m8,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v16, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m8,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v16, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_v16i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement <16 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer + %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i64> %v +} + +define <16 x i64> @vsll_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_v16i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 16, e64,m8,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v16, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m8,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v16 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_v16i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement <16 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i64> %v +} + +define <16 x i64> @vsll_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v16i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i64> undef, i64 3, i32 0 + %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer + %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i64> %v +} + +define <16 x i64> @vsll_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_v16i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i64> undef, i64 3, i32 0 + %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i64> %v +} diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll new file mode 100644 index 0000000..3f78911 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll @@ -0,0 +1,1333 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 + +declare <2 x i8> @llvm.vp.lshr.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32) + +define <2 x i8> @vsrl_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <2 x i8> @llvm.vp.lshr.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + ret <2 x i8> %v +} + +define <2 x i8> @vsrl_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v2i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i8> @llvm.vp.lshr.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + ret <2 x i8> %v +} + +define <2 x i8> @vsrl_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer + %v = call <2 x i8> @llvm.vp.lshr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i8> %v +} + +define <2 x i8> @vsrl_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v2i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i8> @llvm.vp.lshr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i8> %v +} + +define <2 x i8> @vsrl_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i8> undef, i8 4, i32 0 + %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer + %v = call <2 x i8> @llvm.vp.lshr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i8> %v +} + +define <2 x i8> @vsrl_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v2i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i8> undef, i8 4, i32 0 + %vb = shufflevector <2 x i8> %elt.head, <2 x i8> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i8> @llvm.vp.lshr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i8> %v +} + +declare <4 x i8> @llvm.vp.lshr.v4i8(<4 x i8>, <4 x i8>, <4 x i1>, i32) + +define <4 x i8> @vsrl_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v4i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <4 x i8> @llvm.vp.lshr.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + ret <4 x i8> %v +} + +define <4 x i8> @vsrl_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v4i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i8> @llvm.vp.lshr.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + ret <4 x i8> %v +} + +define <4 x i8> @vsrl_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v4i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer + %v = call <4 x i8> @llvm.vp.lshr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i8> %v +} + +define <4 x i8> @vsrl_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v4i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i8> @llvm.vp.lshr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i8> %v +} + +define <4 x i8> @vsrl_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v4i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i8> undef, i8 4, i32 0 + %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer + %v = call <4 x i8> @llvm.vp.lshr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i8> %v +} + +define <4 x i8> @vsrl_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v4i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i8> undef, i8 4, i32 0 + %vb = shufflevector <4 x i8> %elt.head, <4 x i8> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i8> @llvm.vp.lshr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i8> %v +} + +declare <8 x i8> @llvm.vp.lshr.v8i8(<8 x i8>, <8 x i8>, <8 x i1>, i32) + +define <8 x i8> @vsrl_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <8 x i8> @llvm.vp.lshr.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + ret <8 x i8> %v +} + +define <8 x i8> @vsrl_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v8i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i8> @llvm.vp.lshr.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + ret <8 x i8> %v +} + +define <8 x i8> @vsrl_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer + %v = call <8 x i8> @llvm.vp.lshr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i8> %v +} + +define <8 x i8> @vsrl_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v8i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i8> @llvm.vp.lshr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i8> %v +} + +define <8 x i8> @vsrl_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i8> undef, i8 4, i32 0 + %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer + %v = call <8 x i8> @llvm.vp.lshr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i8> %v +} + +define <8 x i8> @vsrl_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v8i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i8> undef, i8 4, i32 0 + %vb = shufflevector <8 x i8> %elt.head, <8 x i8> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i8> @llvm.vp.lshr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i8> %v +} + +declare <16 x i8> @llvm.vp.lshr.v16i8(<16 x i8>, <16 x i8>, <16 x i1>, i32) + +define <16 x i8> @vsrl_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v16i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <16 x i8> @llvm.vp.lshr.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + ret <16 x i8> %v +} + +define <16 x i8> @vsrl_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v16i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i8> @llvm.vp.lshr.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + ret <16 x i8> %v +} + +define <16 x i8> @vsrl_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v16i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer + %v = call <16 x i8> @llvm.vp.lshr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i8> %v +} + +define <16 x i8> @vsrl_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v16i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i8> undef, i8 %b, i32 0 + %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i8> @llvm.vp.lshr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i8> %v +} + +define <16 x i8> @vsrl_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v16i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i8> undef, i8 4, i32 0 + %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer + %v = call <16 x i8> @llvm.vp.lshr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i8> %v +} + +define <16 x i8> @vsrl_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v16i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i8> undef, i8 4, i32 0 + %vb = shufflevector <16 x i8> %elt.head, <16 x i8> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i8> @llvm.vp.lshr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i8> %v +} + +declare <2 x i16> @llvm.vp.lshr.v2i16(<2 x i16>, <2 x i16>, <2 x i1>, i32) + +define <2 x i16> @vsrl_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <2 x i16> @llvm.vp.lshr.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + ret <2 x i16> %v +} + +define <2 x i16> @vsrl_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v2i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i16> @llvm.vp.lshr.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + ret <2 x i16> %v +} + +define <2 x i16> @vsrl_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer + %v = call <2 x i16> @llvm.vp.lshr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i16> %v +} + +define <2 x i16> @vsrl_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v2i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i16> @llvm.vp.lshr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i16> %v +} + +define <2 x i16> @vsrl_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i16> undef, i16 4, i32 0 + %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer + %v = call <2 x i16> @llvm.vp.lshr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i16> %v +} + +define <2 x i16> @vsrl_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v2i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i16> undef, i16 4, i32 0 + %vb = shufflevector <2 x i16> %elt.head, <2 x i16> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i16> @llvm.vp.lshr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i16> %v +} + +declare <4 x i16> @llvm.vp.lshr.v4i16(<4 x i16>, <4 x i16>, <4 x i1>, i32) + +define <4 x i16> @vsrl_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v4i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <4 x i16> @llvm.vp.lshr.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + ret <4 x i16> %v +} + +define <4 x i16> @vsrl_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v4i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i16> @llvm.vp.lshr.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + ret <4 x i16> %v +} + +define <4 x i16> @vsrl_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v4i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer + %v = call <4 x i16> @llvm.vp.lshr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i16> %v +} + +define <4 x i16> @vsrl_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v4i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i16> @llvm.vp.lshr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i16> %v +} + +define <4 x i16> @vsrl_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v4i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i16> undef, i16 4, i32 0 + %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer + %v = call <4 x i16> @llvm.vp.lshr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i16> %v +} + +define <4 x i16> @vsrl_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v4i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i16> undef, i16 4, i32 0 + %vb = shufflevector <4 x i16> %elt.head, <4 x i16> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i16> @llvm.vp.lshr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i16> %v +} + +declare <8 x i16> @llvm.vp.lshr.v8i16(<8 x i16>, <8 x i16>, <8 x i1>, i32) + +define <8 x i16> @vsrl_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <8 x i16> @llvm.vp.lshr.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + ret <8 x i16> %v +} + +define <8 x i16> @vsrl_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v8i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i16> @llvm.vp.lshr.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + ret <8 x i16> %v +} + +define <8 x i16> @vsrl_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer + %v = call <8 x i16> @llvm.vp.lshr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i16> %v +} + +define <8 x i16> @vsrl_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v8i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i16> @llvm.vp.lshr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i16> %v +} + +define <8 x i16> @vsrl_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i16> undef, i16 4, i32 0 + %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer + %v = call <8 x i16> @llvm.vp.lshr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i16> %v +} + +define <8 x i16> @vsrl_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v8i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i16> undef, i16 4, i32 0 + %vb = shufflevector <8 x i16> %elt.head, <8 x i16> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i16> @llvm.vp.lshr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i16> %v +} + +declare <16 x i16> @llvm.vp.lshr.v16i16(<16 x i16>, <16 x i16>, <16 x i1>, i32) + +define <16 x i16> @vsrl_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10, v0.t +; CHECK-NEXT: ret + %v = call <16 x i16> @llvm.vp.lshr.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + ret <16 x i16> %v +} + +define <16 x i16> @vsrl_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v16i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: ret + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i16> @llvm.vp.lshr.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + ret <16 x i16> %v +} + +define <16 x i16> @vsrl_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer + %v = call <16 x i16> @llvm.vp.lshr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i16> %v +} + +define <16 x i16> @vsrl_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v16i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i16> undef, i16 %b, i32 0 + %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i16> @llvm.vp.lshr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i16> %v +} + +define <16 x i16> @vsrl_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i16> undef, i16 4, i32 0 + %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer + %v = call <16 x i16> @llvm.vp.lshr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i16> %v +} + +define <16 x i16> @vsrl_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v16i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i16> undef, i16 4, i32 0 + %vb = shufflevector <16 x i16> %elt.head, <16 x i16> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i16> @llvm.vp.lshr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i16> %v +} + +declare <2 x i32> @llvm.vp.lshr.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32) + +define <2 x i32> @vsrl_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v2i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <2 x i32> @llvm.vp.lshr.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + ret <2 x i32> %v +} + +define <2 x i32> @vsrl_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v2i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i32> @llvm.vp.lshr.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + ret <2 x i32> %v +} + +define <2 x i32> @vsrl_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v2i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer + %v = call <2 x i32> @llvm.vp.lshr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i32> %v +} + +define <2 x i32> @vsrl_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v2i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i32> @llvm.vp.lshr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i32> %v +} + +define <2 x i32> @vsrl_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v2i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i32> undef, i32 4, i32 0 + %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer + %v = call <2 x i32> @llvm.vp.lshr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i32> %v +} + +define <2 x i32> @vsrl_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v2i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i32> undef, i32 4, i32 0 + %vb = shufflevector <2 x i32> %elt.head, <2 x i32> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i32> @llvm.vp.lshr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i32> %v +} + +declare <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32) + +define <4 x i32> @vsrl_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + ret <4 x i32> %v +} + +define <4 x i32> @vsrl_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v4i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + ret <4 x i32> %v +} + +define <4 x i32> @vsrl_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer + %v = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i32> %v +} + +define <4 x i32> @vsrl_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v4i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i32> %v +} + +define <4 x i32> @vsrl_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i32> undef, i32 4, i32 0 + %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer + %v = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i32> %v +} + +define <4 x i32> @vsrl_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v4i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i32> undef, i32 4, i32 0 + %vb = shufflevector <4 x i32> %elt.head, <4 x i32> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i32> %v +} + +declare <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) + +define <8 x i32> @vsrl_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10, v0.t +; CHECK-NEXT: ret + %v = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + ret <8 x i32> %v +} + +define <8 x i32> @vsrl_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v8i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: ret + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + ret <8 x i32> %v +} + +define <8 x i32> @vsrl_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer + %v = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i32> %v +} + +define <8 x i32> @vsrl_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v8i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i32> %v +} + +define <8 x i32> @vsrl_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i32> undef, i32 4, i32 0 + %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer + %v = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i32> %v +} + +define <8 x i32> @vsrl_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v8i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i32> undef, i32 4, i32 0 + %vb = shufflevector <8 x i32> %elt.head, <8 x i32> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i32> %v +} + +declare <16 x i32> @llvm.vp.lshr.v16i32(<16 x i32>, <16 x i32>, <16 x i1>, i32) + +define <16 x i32> @vsrl_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v16i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12, v0.t +; CHECK-NEXT: ret + %v = call <16 x i32> @llvm.vp.lshr.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + ret <16 x i32> %v +} + +define <16 x i32> @vsrl_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v16i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12 +; CHECK-NEXT: ret + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i32> @llvm.vp.lshr.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + ret <16 x i32> %v +} + +define <16 x i32> @vsrl_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v16i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer + %v = call <16 x i32> @llvm.vp.lshr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i32> %v +} + +define <16 x i32> @vsrl_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_v16i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i32> undef, i32 %b, i32 0 + %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i32> @llvm.vp.lshr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i32> %v +} + +define <16 x i32> @vsrl_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v16i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i32> undef, i32 4, i32 0 + %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer + %v = call <16 x i32> @llvm.vp.lshr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i32> %v +} + +define <16 x i32> @vsrl_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v16i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i32> undef, i32 4, i32 0 + %vb = shufflevector <16 x i32> %elt.head, <16 x i32> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i32> @llvm.vp.lshr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i32> %v +} + +declare <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64>, <2 x i64>, <2 x i1>, i32) + +define <2 x i64> @vsrl_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v2i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + ret <2 x i64> %v +} + +define <2 x i64> @vsrl_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v2i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + ret <2 x i64> %v +} + +define <2 x i64> @vsrl_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_v2i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 2, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m1,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v25, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_v2i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement <2 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer + %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i64> %v +} + +define <2 x i64> @vsrl_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_v2i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 2, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m1,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v25 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_v2i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement <2 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i64> %v +} + +define <2 x i64> @vsrl_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v2i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i64> undef, i64 4, i32 0 + %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer + %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i64> %v +} + +define <2 x i64> @vsrl_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v2i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <2 x i64> undef, i64 4, i32 0 + %vb = shufflevector <2 x i64> %elt.head, <2 x i64> undef, <2 x i32> zeroinitializer + %head = insertelement <2 x i1> undef, i1 true, i32 0 + %m = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer + %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + ret <2 x i64> %v +} + +declare <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64>, <4 x i64>, <4 x i1>, i32) + +define <4 x i64> @vsrl_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v4i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10, v0.t +; CHECK-NEXT: ret + %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + ret <4 x i64> %v +} + +define <4 x i64> @vsrl_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v4i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: ret + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + ret <4 x i64> %v +} + +define <4 x i64> @vsrl_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_v4i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 4, e64,m2,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m2,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v26, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_v4i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement <4 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer + %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i64> %v +} + +define <4 x i64> @vsrl_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_v4i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 4, e64,m2,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m2,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v26 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_v4i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement <4 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i64> %v +} + +define <4 x i64> @vsrl_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v4i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i64> undef, i64 4, i32 0 + %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer + %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i64> %v +} + +define <4 x i64> @vsrl_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v4i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <4 x i64> undef, i64 4, i32 0 + %vb = shufflevector <4 x i64> %elt.head, <4 x i64> undef, <4 x i32> zeroinitializer + %head = insertelement <4 x i1> undef, i1 true, i32 0 + %m = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer + %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + ret <4 x i64> %v +} + +declare <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64>, <8 x i64>, <8 x i1>, i32) + +define <8 x i64> @vsrl_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v8i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12, v0.t +; CHECK-NEXT: ret + %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + ret <8 x i64> %v +} + +define <8 x i64> @vsrl_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v8i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12 +; CHECK-NEXT: ret + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + ret <8 x i64> %v +} + +define <8 x i64> @vsrl_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_v8i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 8, e64,m4,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m4,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v28, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_v8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement <8 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer + %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i64> %v +} + +define <8 x i64> @vsrl_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_v8i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 8, e64,m4,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m4,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v28 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_v8i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement <8 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i64> %v +} + +define <8 x i64> @vsrl_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v8i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i64> undef, i64 4, i32 0 + %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer + %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i64> %v +} + +define <8 x i64> @vsrl_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v8i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <8 x i64> undef, i64 4, i32 0 + %vb = shufflevector <8 x i64> %elt.head, <8 x i64> undef, <8 x i32> zeroinitializer + %head = insertelement <8 x i1> undef, i1 true, i32 0 + %m = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer + %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + ret <8 x i64> %v +} + +declare <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64>, <16 x i64>, <16 x i1>, i32) + +define <16 x i64> @vsrl_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v16i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16, v0.t +; CHECK-NEXT: ret + %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + ret <16 x i64> %v +} + +define <16 x i64> @vsrl_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_v16i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16 +; CHECK-NEXT: ret + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + ret <16 x i64> %v +} + +define <16 x i64> @vsrl_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_v16i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 16, e64,m8,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v16, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m8,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v16, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_v16i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement <16 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer + %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i64> %v +} + +define <16 x i64> @vsrl_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_v16i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetivli a0, 16, e64,m8,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v16, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m8,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v16 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_v16i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement <16 x i64> undef, i64 %b, i32 0 + %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i64> %v +} + +define <16 x i64> @vsrl_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v16i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i64> undef, i64 4, i32 0 + %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer + %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i64> %v +} + +define <16 x i64> @vsrl_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_v16i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement <16 x i64> undef, i64 4, i32 0 + %vb = shufflevector <16 x i64> %elt.head, <16 x i64> undef, <16 x i32> zeroinitializer + %head = insertelement <16 x i1> undef, i1 true, i32 0 + %m = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer + %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + ret <16 x i64> %v +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll new file mode 100644 index 0000000..6d77d42 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll @@ -0,0 +1,1789 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 + +declare @llvm.vp.shl.nxv1i8(, , , i32) + +define @vsll_vv_nxv1i8( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv1i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv1i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv1i8_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv1i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv1i8( %va, i8 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv1i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv1i8_unmasked( %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv1i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv1i8( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv1i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv1i8_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv1i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i8( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv2i8(, , , i32) + +define @vsll_vv_nxv2i8( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv2i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv2i8_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv2i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv2i8( %va, i8 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv2i8_unmasked( %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv2i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv2i8( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv2i8_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv2i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i8( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv4i8(, , , i32) + +define @vsll_vv_nxv4i8( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv4i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv4i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv4i8_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv4i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv4i8( %va, i8 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv4i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv4i8_unmasked( %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv4i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv4i8( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv4i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv4i8_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv4i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i8( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv8i8(, , , i32) + +define @vsll_vv_nxv8i8( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv8i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv8i8_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv8i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv8i8( %va, i8 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv8i8_unmasked( %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv8i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv8i8( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv8i8_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv8i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i8( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv16i8(, , , i32) + +define @vsll_vv_nxv16i8( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv16i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv16i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv16i8_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv16i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv16i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv16i8( %va, i8 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv16i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv16i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv16i8_unmasked( %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv16i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv16i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv16i8( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv16i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv16i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv16i8_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv16i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv16i8( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv32i8(, , , i32) + +define @vsll_vv_nxv32i8( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv32i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv32i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv32i8_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv32i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv32i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv32i8( %va, i8 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv32i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv32i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv32i8_unmasked( %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv32i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv32i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv32i8( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv32i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv32i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv32i8_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv32i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv32i8( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv64i8(, , , i32) + +define @vsll_vv_nxv64i8( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv64i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv64i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv64i8_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv64i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv64i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv64i8( %va, i8 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv64i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv64i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv64i8_unmasked( %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv64i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv64i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv64i8( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv64i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv64i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv64i8_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv64i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv64i8( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv1i16(, , , i32) + +define @vsll_vv_nxv1i16( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv1i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv1i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv1i16_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv1i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv1i16( %va, i16 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv1i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv1i16_unmasked( %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv1i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv1i16( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv1i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv1i16_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv1i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i16( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv2i16(, , , i32) + +define @vsll_vv_nxv2i16( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv2i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv2i16_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv2i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv2i16( %va, i16 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv2i16_unmasked( %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv2i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv2i16( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv2i16_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv2i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i16( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv4i16(, , , i32) + +define @vsll_vv_nxv4i16( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv4i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv4i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv4i16_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv4i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv4i16( %va, i16 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv4i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv4i16_unmasked( %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv4i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv4i16( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv4i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv4i16_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv4i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i16( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv8i16(, , , i32) + +define @vsll_vv_nxv8i16( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv8i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv8i16_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv8i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv8i16( %va, i16 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv8i16_unmasked( %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv8i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv8i16( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv8i16_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv8i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i16( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv16i16(, , , i32) + +define @vsll_vv_nxv16i16( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv16i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv16i16_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv16i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv16i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv16i16( %va, i16 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv16i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv16i16_unmasked( %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv16i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv16i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv16i16( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv16i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv16i16_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv16i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv16i16( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv32i16(, , , i32) + +define @vsll_vv_nxv32i16( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv32i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv32i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv32i16_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv32i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv32i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv32i16( %va, i16 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv32i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv32i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv32i16_unmasked( %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv32i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv32i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv32i16( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv32i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv32i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv32i16_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv32i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv32i16( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv1i32(, , , i32) + +define @vsll_vv_nxv1i32( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv1i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv1i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv1i32_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv1i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv1i32( %va, i32 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv1i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv1i32_unmasked( %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv1i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv1i32( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv1i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv1i32_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv1i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i32( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv2i32(, , , i32) + +define @vsll_vv_nxv2i32( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv2i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv2i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv2i32_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv2i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv2i32( %va, i32 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv2i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv2i32_unmasked( %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv2i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv2i32( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv2i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv2i32_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv2i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i32( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv4i32(, , , i32) + +define @vsll_vv_nxv4i32( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv4i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv4i32_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv4i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv4i32( %va, i32 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv4i32_unmasked( %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv4i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv4i32( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv4i32_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv4i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i32( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv8i32(, , , i32) + +define @vsll_vv_nxv8i32( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv8i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv8i32_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv8i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv8i32( %va, i32 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv8i32_unmasked( %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv8i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv8i32( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv8i32_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv8i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i32( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv16i32(, , , i32) + +define @vsll_vv_nxv16i32( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv16i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv16i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv16i32_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv16i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv16i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv16i32( %va, i32 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv16i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv16i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv16i32_unmasked( %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vx_nxv16i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv16i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv16i32( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv16i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv16i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv16i32_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv16i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv16i32( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv1i64(, , , i32) + +define @vsll_vv_nxv1i64( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv1i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv1i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv1i64_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv1i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv1i64( %va, i64 %b, %m, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_nxv1i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m1,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v25, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_nxv1i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv1i64_unmasked( %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_nxv1i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m1,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v25 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_nxv1i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv1i64( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv1i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv1i64_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv1i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv1i64( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv2i64(, , , i32) + +define @vsll_vv_nxv2i64( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv2i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv2i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv2i64_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv2i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv2i64( %va, i64 %b, %m, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_nxv2i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m2,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v26, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_nxv2i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv2i64_unmasked( %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_nxv2i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m2,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v26 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_nxv2i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv2i64( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv2i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv2i64_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv2i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv2i64( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv4i64(, , , i32) + +define @vsll_vv_nxv4i64( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv4i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv4i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv4i64_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv4i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv4i64( %va, i64 %b, %m, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_nxv4i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m4,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v28, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_nxv4i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv4i64_unmasked( %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_nxv4i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m4,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v28 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_nxv4i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv4i64( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv4i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv4i64_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv4i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv4i64( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.shl.nxv8i64(, , , i32) + +define @vsll_vv_nxv8i64( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv8i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.shl.nxv8i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vv_nxv8i64_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vv_nxv8i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv8i64( %va, i64 %b, %m, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v16, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m8,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v16, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vx_nxv8i64_unmasked( %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsll_vx_nxv8i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v16, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m8,ta,mu +; RV32-NEXT: vsll.vv v8, v8, v16 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsll_vx_nxv8i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; RV64-NEXT: vsll.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv8i64( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv8i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsll_vi_nxv8i64_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsll_vi_nxv8i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 3 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 3, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.shl.nxv8i64( %va, %vb, %m, i32 %evl) + ret %v +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll new file mode 100644 index 0000000..62f3353 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll @@ -0,0 +1,1789 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 + +declare @llvm.vp.lshr.nxv1i8(, , , i32) + +define @vsrl_vv_nxv1i8( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv1i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv1i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv1i8_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv1i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv1i8( %va, i8 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv1i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv1i8_unmasked( %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv1i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv1i8( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv1i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv1i8_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv1i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i8( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv2i8(, , , i32) + +define @vsrl_vv_nxv2i8( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv2i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv2i8_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv2i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv2i8( %va, i8 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv2i8_unmasked( %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv2i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv2i8( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv2i8_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv2i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i8( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv4i8(, , , i32) + +define @vsrl_vv_nxv4i8( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv4i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv4i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv4i8_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv4i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv4i8( %va, i8 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv4i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv4i8_unmasked( %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv4i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv4i8( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv4i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv4i8_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv4i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i8( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv8i8(, , , i32) + +define @vsrl_vv_nxv8i8( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv8i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv8i8_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv8i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv8i8( %va, i8 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv8i8_unmasked( %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv8i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv8i8( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv8i8_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv8i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i8( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv16i8(, , , i32) + +define @vsrl_vv_nxv16i8( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv16i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv16i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv16i8_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv16i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv16i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv16i8( %va, i8 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv16i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv16i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv16i8_unmasked( %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv16i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv16i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv16i8( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv16i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv16i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv16i8_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv16i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv16i8( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv32i8(, , , i32) + +define @vsrl_vv_nxv32i8( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv32i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv32i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv32i8_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv32i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv32i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv32i8( %va, i8 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv32i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv32i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv32i8_unmasked( %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv32i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv32i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv32i8( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv32i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv32i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv32i8_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv32i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv32i8( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv64i8(, , , i32) + +define @vsrl_vv_nxv64i8( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv64i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv64i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv64i8_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv64i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv64i8( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv64i8( %va, i8 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv64i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv64i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv64i8_unmasked( %va, i8 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv64i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv64i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv64i8( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv64i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv64i8( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv64i8_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv64i8_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i8 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv64i8( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv1i16(, , , i32) + +define @vsrl_vv_nxv1i16( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv1i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv1i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv1i16_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv1i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv1i16( %va, i16 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv1i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv1i16_unmasked( %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv1i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv1i16( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv1i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv1i16_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv1i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i16( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv2i16(, , , i32) + +define @vsrl_vv_nxv2i16( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv2i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv2i16_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv2i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv2i16( %va, i16 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv2i16_unmasked( %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv2i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv2i16( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv2i16_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv2i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i16( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv4i16(, , , i32) + +define @vsrl_vv_nxv4i16( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv4i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv4i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv4i16_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv4i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv4i16( %va, i16 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv4i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv4i16_unmasked( %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv4i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv4i16( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv4i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv4i16_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv4i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i16( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv8i16(, , , i32) + +define @vsrl_vv_nxv8i16( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv8i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv8i16_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv8i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv8i16( %va, i16 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv8i16_unmasked( %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv8i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv8i16( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv8i16_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv8i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i16( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv16i16(, , , i32) + +define @vsrl_vv_nxv16i16( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv16i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv16i16_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv16i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv16i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv16i16( %va, i16 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv16i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv16i16_unmasked( %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv16i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv16i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv16i16( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv16i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv16i16_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv16i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv16i16( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv32i16(, , , i32) + +define @vsrl_vv_nxv32i16( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv32i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv32i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv32i16_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv32i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv32i16( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv32i16( %va, i16 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv32i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv32i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv32i16_unmasked( %va, i16 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv32i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv32i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv32i16( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv32i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv32i16( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv32i16_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv32i16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i16 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv32i16( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv1i32(, , , i32) + +define @vsrl_vv_nxv1i32( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv1i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv1i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv1i32_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv1i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv1i32( %va, i32 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv1i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv1i32_unmasked( %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv1i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv1i32( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv1i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv1i32_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv1i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i32( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv2i32(, , , i32) + +define @vsrl_vv_nxv2i32( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv2i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv2i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv2i32_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv2i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv2i32( %va, i32 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv2i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv2i32_unmasked( %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv2i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv2i32( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv2i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv2i32_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv2i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i32( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv4i32(, , , i32) + +define @vsrl_vv_nxv4i32( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv4i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv4i32_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv4i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv4i32( %va, i32 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv4i32_unmasked( %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv4i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv4i32( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv4i32_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv4i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i32( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv8i32(, , , i32) + +define @vsrl_vv_nxv8i32( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv8i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv8i32_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv8i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv8i32( %va, i32 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv8i32_unmasked( %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv8i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv8i32( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv8i32_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv8i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i32( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv16i32(, , , i32) + +define @vsrl_vv_nxv16i32( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv16i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv16i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv16i32_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv16i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv16i32( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv16i32( %va, i32 %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv16i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv16i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv16i32_unmasked( %va, i32 %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vx_nxv16i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv16i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv16i32( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv16i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv16i32( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv16i32_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv16i32_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i32 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv16i32( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv1i64(, , , i32) + +define @vsrl_vv_nxv1i64( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv1i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv1i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv1i64_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv1i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv1i64( %va, i64 %b, %m, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_nxv1i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m1,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v25, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_nxv1i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv1i64_unmasked( %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_nxv1i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m1,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v25, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m1,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v25 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_nxv1i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv1i64( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv1i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv1i64_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv1i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv1i64( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv2i64(, , , i32) + +define @vsrl_vv_nxv2i64( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv2i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv2i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv2i64_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv2i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv2i64( %va, i64 %b, %m, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_nxv2i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m2,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v26, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_nxv2i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv2i64_unmasked( %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_nxv2i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m2,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v26, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m2,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v26 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_nxv2i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv2i64( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv2i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv2i64_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv2i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv2i64( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv4i64(, , , i32) + +define @vsrl_vv_nxv4i64( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv4i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv4i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv4i64_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv4i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv4i64( %va, i64 %b, %m, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_nxv4i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m4,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v28, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_nxv4i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv4i64_unmasked( %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_nxv4i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m4,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v28, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m4,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v28 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_nxv4i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv4i64( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv4i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv4i64_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv4i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv4i64( %va, %vb, %m, i32 %evl) + ret %v +} + +declare @llvm.vp.lshr.nxv8i64(, , , i32) + +define @vsrl_vv_nxv8i64( %va, %b, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv8i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16, v0.t +; CHECK-NEXT: ret + %v = call @llvm.vp.lshr.nxv8i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vv_nxv8i64_unmasked( %va, %b, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vv_nxv8i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16 +; CHECK-NEXT: ret + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i64( %va, %b, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv8i64( %va, i64 %b, %m, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_nxv8i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v16, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m8,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v16, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_nxv8i64: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vx_nxv8i64_unmasked( %va, i64 %b, i32 zeroext %evl) { +; RV32-LABEL: vsrl_vx_nxv8i64_unmasked: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vlse64.v v16, (a0), zero +; RV32-NEXT: vsetvli a0, a2, e64,m8,ta,mu +; RV32-NEXT: vsrl.vv v8, v8, v16 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsrl_vx_nxv8i64_unmasked: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; RV64-NEXT: vsrl.vx v8, v8, a0 +; RV64-NEXT: ret + %elt.head = insertelement undef, i64 %b, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv8i64( %va, %m, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv8i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i64( %va, %vb, %m, i32 %evl) + ret %v +} + +define @vsrl_vi_nxv8i64_unmasked( %va, i32 zeroext %evl) { +; CHECK-LABEL: vsrl_vi_nxv8i64_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 4 +; CHECK-NEXT: ret + %elt.head = insertelement undef, i64 4, i32 0 + %vb = shufflevector %elt.head, undef, zeroinitializer + %head = insertelement undef, i1 true, i32 0 + %m = shufflevector %head, undef, zeroinitializer + %v = call @llvm.vp.lshr.nxv8i64( %va, %vb, %m, i32 %evl) + ret %v +}