From: Wolfgang Wallner Date: Tue, 21 Jul 2020 11:01:45 +0000 (+0200) Subject: x86: irq: Fix some typos X-Git-Tag: v2020.10~84^2~4 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=491135805e087d4aa05aed1c53722154d8ec5ad2;p=platform%2Fkernel%2Fu-boot.git x86: irq: Fix some typos Fix some typos in arch/x86/include/asm/irq.h. Signed-off-by: Wolfgang Wallner Reviewed-by: Bin Meng --- diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index e5c9160..bee0760 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -12,8 +12,8 @@ * Intel interrupt router configuration mechanism * * There are two known ways of Intel interrupt router configuration mechanism - * so far. On most cases, the IRQ routing configuraiton is controlled by PCI - * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0). + * so far. On most cases, the IRQ routing configuration is controlled by PCI + * configuration registers on the legacy bridge, normally PCI BDF(0, 31, 0). * On some newer platforms like BayTrail and Braswell, the IRQ routing is now * in the IBASE register block where IBASE is memory-mapped. */ @@ -36,7 +36,7 @@ struct pirq_regmap { * @link_base: link value base number * @link_num: number of PIRQ links supported * @has_regmap: has mapping table between PIRQ link and routing register offset - * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means + * @irq_mask: IRQ mask representing the 16 IRQs in 8259, bit N is 1 means * IRQ N is available to be routed * @lb_bdf: irq router's PCI bus/device/function number encoding * @ibase: IBASE register block base address