From: Peter Maydell Date: Wed, 30 Mar 2016 15:06:44 +0000 (+0100) Subject: Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160329-2' into staging X-Git-Tag: TizenStudio_2.0_p2.4~27^2~6^2~8^2~82 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=489ef4c810033e63af570c8a430af8b9858bfa5f;p=sdk%2Femulator%2Fqemu.git Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160329-2' into staging MIPS patches 2016-03-29 Changes: * add initial MIPS CPS support * implement ITU block * implement MAAR # gpg: Signature made Wed 30 Mar 2016 09:27:01 BST using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae " * remotes/lalrae/tags/mips-20160329-2: (21 commits) target-mips: add MAAR, MAARI register target-mips: use CP0_CHECK for gen_m{f|t}hc0 hw/mips/cps: enable ITU for multithreading processors target-mips: make ITC Configuration Tags accessible to the CPU target-mips: check CP0 enabled for CACHE instruction also in R6 hw/mips: implement ITC Storage - Bypass View hw/mips: implement ITC Storage - P/V Sync and Try Views hw/mips: implement ITC Storage - Empty/Full Sync and Try Views hw/mips: implement ITC Storage - Control View hw/mips: implement ITC Configuration Tags and Storage Cells target-mips: enable CM GCR in MIPS64R6-generic CPU hw/mips_malta: add CPS to Malta board hw/mips_malta: move CPU creation to a separate function hw/mips_malta: remove redundant irq and clock init hw/mips_malta: remove CPUMIPSState from the write_bootloader() hw/mips/cps: create CPC block inside CPS hw/mips: add initial Cluster Power Controller support hw/mips/cps: create GCR block inside CPS hw/mips: add initial Global Config Register support target-mips: add CMGCRBase register ... Signed-off-by: Peter Maydell --- 489ef4c810033e63af570c8a430af8b9858bfa5f