From: Duncan Laurie <dlaurie@chromium.org>
Date: Mon, 3 Dec 2012 13:59:00 +0000 (+0000)
Subject: x86: Fix MTRR clear to detect which MTRR to use
X-Git-Tag: v2013.01-rc2~73^2~11
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=488b8b242b72fe551dc38e33af8c7f94747610bd;p=kernel%2Fu-boot.git

x86: Fix MTRR clear to detect which MTRR to use

Coreboot was always using MTRR 7 for the write-protect
cache entry that covers the ROM and U-boot was removing it.
However with 4GB configs we need more MTRRs for the BIOS
and so the WP MTRR needs to move.  Instead coreboot will
always use the last available MTRR that is normally set
aside for OS use and U-boot can clear it before the OS.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
---

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 5a4c3e5..f73977f 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -94,6 +94,8 @@ void setup_pcat_compatibility()
 {
 }
 
+#define MTRR_TYPE_WP          5
+#define MTRRcap_MSR           0xfe
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 
@@ -101,11 +103,20 @@ int board_final_cleanup(void)
 {
 	/* Un-cache the ROM so the kernel has one
 	 * more MTRR available.
+	 *
+	 * Coreboot should have assigned this to the
+	 * top available variable MTRR.
 	 */
-	disable_caches();
-	wrmsrl(MTRRphysBase_MSR(7), 0);
-	wrmsrl(MTRRphysMask_MSR(7), 0);
-	enable_caches();
+	u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1;
+	u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff;
+
+	/* Make sure this MTRR is the correct Write-Protected type */
+	if (top_type == MTRR_TYPE_WP) {
+		disable_caches();
+		wrmsrl(MTRRphysBase_MSR(top_mtrr), 0);
+		wrmsrl(MTRRphysMask_MSR(top_mtrr), 0);
+		enable_caches();
+	}
 
 	return 0;
 }