From: Mandeep Singh Grang <mgrang@codeaurora.org>
Date: Thu, 16 Nov 2017 20:30:49 +0000 (+0000)
Subject: [RISCV] Fix 64-bit data layout mismatch between backend and target description
X-Git-Tag: llvmorg-6.0.0-rc1~3191
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=47fbc5911dca29ca64eb8d3500d382dde7921975;p=platform%2Fupstream%2Fllvm.git

[RISCV] Fix 64-bit data layout mismatch between backend and target description

Reviewers: asb

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, llvm-commits

Differential Revision: https://reviews.llvm.org/D40145

llvm-svn: 318454
---

diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 34da6de..e12168b 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -30,7 +30,7 @@ extern "C" void LLVMInitializeRISCVTarget() {
 
 static std::string computeDataLayout(const Triple &TT) {
   if (TT.isArch64Bit()) {
-    return "e-m:e-i64:64-n32:64-S128";
+    return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
   } else {
     assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
     return "e-m:e-p:32:32-i64:64-n32-S128";