From: Eric Anholt <eric@anholt.net>
Date: Wed, 1 Nov 2017 22:28:04 +0000 (-0700)
Subject: broadcom/vc5: Fix translation of stencil ops.
X-Git-Tag: upstream/18.1.0~4438
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=47bd9dac197ab47313cfb48a60f7a9e3a2ac3877;p=platform%2Fupstream%2Fmesa.git

broadcom/vc5: Fix translation of stencil ops.

They aren't quite in the same order as the gallium defines.  Fixes piglit
gl-2.0-two-sided-stencil.
---

diff --git a/src/gallium/drivers/vc5/vc5_context.h b/src/gallium/drivers/vc5/vc5_context.h
index dcaf45a..298dfac 100644
--- a/src/gallium/drivers/vc5/vc5_context.h
+++ b/src/gallium/drivers/vc5/vc5_context.h
@@ -395,8 +395,8 @@ struct vc5_depth_stencil_alpha_state {
          */
         uint32_t stencil_uniforms[3];
 
-        uint8_t stencil_front[8];
-        uint8_t stencil_back[8];
+        uint8_t stencil_front[6];
+        uint8_t stencil_back[6];
 };
 
 #define perf_debug(...) do {                            \
diff --git a/src/gallium/drivers/vc5/vc5_state.c b/src/gallium/drivers/vc5/vc5_state.c
index 2a8393e..d885553 100644
--- a/src/gallium/drivers/vc5/vc5_state.c
+++ b/src/gallium/drivers/vc5/vc5_state.c
@@ -127,6 +127,22 @@ vc5_create_blend_state(struct pipe_context *pctx,
         return vc5_generic_cso_state_create(cso, sizeof(*cso));
 }
 
+static uint32_t
+translate_stencil_op(enum pipe_stencil_op op)
+{
+        switch (op) {
+        case PIPE_STENCIL_OP_KEEP:      return V3D_STENCIL_OP_KEEP;
+        case PIPE_STENCIL_OP_ZERO:      return V3D_STENCIL_OP_ZERO;
+        case PIPE_STENCIL_OP_REPLACE:   return V3D_STENCIL_OP_REPLACE;
+        case PIPE_STENCIL_OP_INCR:      return V3D_STENCIL_OP_INCR;
+        case PIPE_STENCIL_OP_DECR:      return V3D_STENCIL_OP_DECR;
+        case PIPE_STENCIL_OP_INCR_WRAP: return V3D_STENCIL_OP_INCWRAP;
+        case PIPE_STENCIL_OP_DECR_WRAP: return V3D_STENCIL_OP_DECWRAP;
+        case PIPE_STENCIL_OP_INVERT:    return V3D_STENCIL_OP_INVERT;
+        }
+        unreachable("bad stencil op");
+}
+
 static void *
 vc5_create_depth_stencil_alpha_state(struct pipe_context *pctx,
                                      const struct pipe_depth_stencil_alpha_state *cso)
@@ -168,9 +184,12 @@ vc5_create_depth_stencil_alpha_state(struct pipe_context *pctx,
                         config.stencil_test_mask = front->valuemask;
 
                         config.stencil_test_function = front->func;
-                        config.stencil_pass_op = front->zpass_op;
-                        config.depth_test_fail_op = front->zfail_op;
-                        config.stencil_test_fail_op = front->fail_op;
+                        config.stencil_pass_op =
+                                translate_stencil_op(front->zpass_op);
+                        config.depth_test_fail_op =
+                                translate_stencil_op(front->zfail_op);
+                        config.stencil_test_fail_op =
+                                translate_stencil_op(front->fail_op);
                 }
         }
         if (back->enabled) {
@@ -182,9 +201,12 @@ vc5_create_depth_stencil_alpha_state(struct pipe_context *pctx,
                         config.stencil_test_mask = back->valuemask;
 
                         config.stencil_test_function = back->func;
-                        config.stencil_pass_op = back->zpass_op;
-                        config.depth_test_fail_op = back->zfail_op;
-                        config.stencil_test_fail_op = back->fail_op;
+                        config.stencil_pass_op =
+                                translate_stencil_op(back->zpass_op);
+                        config.depth_test_fail_op =
+                                translate_stencil_op(back->zfail_op);
+                        config.stencil_test_fail_op =
+                                translate_stencil_op(back->fail_op);
                 }
         }