From: Marc Zyngier Date: Fri, 21 Jun 2013 12:08:47 +0000 (+0100) Subject: ARM: KVM: add missing dsb before invalidating Stage-2 TLBs X-Git-Tag: v3.12-rc1~503^2~7^2~4 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=479c5ae2f8a55509b691494cd13691d3dc31d102;p=kernel%2Fkernel-generic.git ARM: KVM: add missing dsb before invalidating Stage-2 TLBs When performing a Stage-2 TLB invalidation, it is necessary to make sure the write to the page tables is observable by all CPUs. For this purpose, add a dsb instruction to __kvm_tlb_flush_vmid_ipa before doing the TLB invalidation itself. Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S index d0a8fa3..20e03d9 100644 --- a/arch/arm/kvm/interrupts.S +++ b/arch/arm/kvm/interrupts.S @@ -49,6 +49,7 @@ __kvm_hyp_code_start: ENTRY(__kvm_tlb_flush_vmid_ipa) push {r2, r3} + dsb ishst add r0, r0, #KVM_VTTBR ldrd r2, r3, [r0] mcrr p15, 6, r2, r3, c2 @ Write VTTBR