From: Sayed Adel <seiko@imavr.com>
Date: Sun, 29 Jul 2018 16:22:46 +0000 (+0200)
Subject: core:avx2 fix unaligned store for v_store_interleave v_uint32x8-3ch
X-Git-Tag: accepted/tizen/6.0/unified/20201030.111113~1^2~597^2~14^2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=47202b3349cad9df1e62978a8280fba266ae487d;hp=9076bb6089b4938d66382f4f36edd5b8ccd73454;p=platform%2Fupstream%2Fopencv.git

core:avx2 fix unaligned store for v_store_interleave v_uint32x8-3ch
---

diff --git a/modules/core/include/opencv2/core/hal/intrin_avx.hpp b/modules/core/include/opencv2/core/hal/intrin_avx.hpp
index 5c2d0b6..fc2fd7c 100644
--- a/modules/core/include/opencv2/core/hal/intrin_avx.hpp
+++ b/modules/core/include/opencv2/core/hal/intrin_avx.hpp
@@ -2156,9 +2156,9 @@ inline void v_store_interleave( unsigned* ptr, const v_uint32x8& b, const v_uint
     }
     else
     {
-        _mm256_stream_si256((__m256i*)ptr, bgr0);
-        _mm256_stream_si256((__m256i*)(ptr + 8), p2);
-        _mm256_stream_si256((__m256i*)(ptr + 16), bgr2);
+        _mm256_storeu_si256((__m256i*)ptr, bgr0);
+        _mm256_storeu_si256((__m256i*)(ptr + 8), p2);
+        _mm256_storeu_si256((__m256i*)(ptr + 16), bgr2);
     }
 }