From: Imre Deak <imre.deak@intel.com>
Date: Tue, 6 Mar 2012 19:17:14 +0000 (+0200)
Subject: gfx: drv: move macro to check pipe validity to psb_intel_reg.h
X-Git-Tag: 2.1b_release~240
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=46fc708949d69479e58e83ba6132a2f9a091ae7f;p=kernel%2Fkernel-mfld-blackbay.git

gfx: drv: move macro to check pipe validity to psb_intel_reg.h

This will be needed by the next patch converting other pipe specific
register definitions in psb_intel_reg.h to use this macro.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
---

diff --git a/drivers/staging/mrst/drv/mdfld_dsi_output.h b/drivers/staging/mrst/drv/mdfld_dsi_output.h
index 3a48255..ca100f5 100644
--- a/drivers/staging/mrst/drv/mdfld_dsi_output.h
+++ b/drivers/staging/mrst/drv/mdfld_dsi_output.h
@@ -30,6 +30,7 @@
 
 #include <linux/backlight.h>
 #include <linux/version.h>
+#include <linux/bitops.h>
 #include <drm/drmP.h>
 #include <drm/drm.h>
 #include <drm/drm_crtc.h>
@@ -45,19 +46,13 @@
 
 #define MDFLD_DSI_BRIGHTNESS_MAX_LEVEL 100
 
-#ifdef DEBUG
-#define CHECK_PIPE(pipe) ({			\
-	const typeof(pipe) __pipe = (pipe);	\
-	BUG_ON(__pipe != 0 && __pipe != 2);	\
-	__pipe;	})
-#else
-#define CHECK_PIPE(pipe) (pipe)
-#endif
-
 /*
  * Actual MIPIA->MIPIC reg offset is 0x800, value 0x400 is valid for 0 and 2
  */
-#define REG_OFFSET(pipe) (CHECK_PIPE(pipe) * 0x400)
+#define CHECK_MIPI_PIPE(pipe)		\
+	(PSB_CHECK_PIPE(pipe, BIT(0) | BIT(2)))
+
+#define REG_OFFSET(pipe)			(CHECK_MIPI_PIPE(pipe) * 0x400)
 
 /* mdfld DSI controller registers */
 #define MIPI_DEVICE_READY_REG(pipe)		(0xb000 + REG_OFFSET(pipe))
@@ -102,7 +97,8 @@
 #define MIPI_CMD_LEN_REG(pipe)			(0xb114 + REG_OFFSET(pipe))
 
 /* non-uniform reg offset */
-#define MIPI_PORT_CONTROL(pipe)		(CHECK_PIPE(pipe) ? MIPI_C : MIPI)
+#define MIPI_PORT_CONTROL(pipe)		\
+		(CHECK_MIPI_PIPE(pipe) ? MIPI_C : MIPI)
 
 #define DSI_DEVICE_READY 					(0x1)
 #define DSI_POWER_STATE_ULPS_ENTER			(0x2 << 1)
diff --git a/drivers/staging/mrst/drv/psb_intel_reg.h b/drivers/staging/mrst/drv/psb_intel_reg.h
index b734f77..eaf3b44 100644
--- a/drivers/staging/mrst/drv/psb_intel_reg.h
+++ b/drivers/staging/mrst/drv/psb_intel_reg.h
@@ -17,6 +17,15 @@
 #ifndef __PSB_INTEL_REG_H__
 #define __PSB_INTEL_REG_H__
 
+#ifdef DEBUG
+#define PSB_CHECK_PIPE(pipe, valid_pipes) ({		\
+	const typeof(pipe) __pipe = (pipe);		\
+	BUG_ON(!((1 << __pipe) & (valid_pipes)));	\
+	__pipe;	})
+#else
+#define PSB_CHECK_PIPE(pipe, valid_pipes) (pipe)
+#endif
+
 #define BLC_PWM_CTL		0x61254
 #define BLC_PWM_CTL2		0x61250
 #define BLC_PWM_CTL_C		0x62254