From: Roman Tereshin <rtereshin@apple.com>
Date: Mon, 30 Apr 2018 18:58:57 +0000 (+0000)
Subject: [MIR] Reset unique MBB numbering in MachineFunction::reset()
X-Git-Tag: llvmorg-7.0.0-rc1~7058
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=46f838f3707183682fe0cd78601e85e089c35aa3;p=platform%2Fupstream%2Fllvm.git

[MIR] Reset unique MBB numbering in MachineFunction::reset()

No need to waste space nor number MBBs differently if MF gets recreated.

Reviewers: qcolombet, stoklund, t.p.northover, bogner, javed.absar

Reviewed By: qcolombet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46078

llvm-svn: 331213
---

diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index fa38a97..e47aeb6 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -196,6 +196,7 @@ void MachineFunction::clear() {
   // Do call MachineBasicBlock destructors, it contains std::vectors.
   for (iterator I = begin(), E = end(); I != E; I = BasicBlocks.erase(I))
     I->Insts.clearAndLeakNodesUnsafely();
+  MBBNumbering.clear();
 
   InstructionRecycler.clear(Allocator);
   OperandRecycler.clear(Allocator);
diff --git a/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir b/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir
index 4d4b93e..324678b 100644
--- a/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir
@@ -14,6 +14,7 @@
 # 5) It's possible to start llc mid-GlobalISel pipeline from a MIR file with
 #    the FailedISel property set to true and watch it properly fallback to
 #    FastISel / SelectionDAG ISel.
+# 6) Resetting a MachineFunction resets unique MachineBasicBlock IDs as well.
 --- |
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64--"
@@ -40,17 +41,21 @@ regBankSelected: true
 failedISel:      true
 tracksRegLiveness: true
 body:             |
-  bb.1.entry:
+  bb.0.entry:
     liveins: $w0, $w1
 
     ; CHECK: liveins: $w0, $w1
+    ;
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
     ; CHECK: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY1]], [[COPY]]
     ; CHECK: $w0 = COPY [[ADD]](s32)
     ; CHECK: RET_ReallyLR implicit $w0
     ;
-    ; FALLBACK: liveins: $w0, $w1
+    ; FALLBACK: body: |
+    ; FALLBACK-NEXT: bb.0.entry:
+    ; FALLBACK-NEXT: liveins: $w0, $w1
+    ;
     ; FALLBACK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
     ; FALLBACK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
     ; FALLBACK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]