From: Tudor Ambarus Date: Tue, 28 Mar 2023 10:15:16 +0000 (+0000) Subject: ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency X-Git-Tag: v6.6.7~3035^2~34^2~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=46a8a137d8f60929923a609cdddde06e7007b0df;p=platform%2Fkernel%2Flinux-starfive.git ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency sama5d2_icp populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~37%. Signed-off-by: Tudor Ambarus Tested-by: Nicolas Ferre # on sama5d2 ICP Link: https://lore.kernel.org/r/20230328101517.1595738-4-tudor.ambarus@linaro.org Signed-off-by: Nicolas Ferre --- diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts index 1346b8f..999adec 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -669,7 +669,8 @@ #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <80000000>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = <7>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read;