From: Dave Airlie <airliedfreedesktop.org>
Date: Thu, 29 Dec 2005 00:56:01 +0000 (+0000)
Subject: add support for PCIE card to EGL, doesn't fully work yet but these changes
X-Git-Tag: 062012170305~21542
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=456a513daa2165b1cc04ef06939384f964d13628;p=profile%2Fivi%2Fmesa.git

add support for PCIE card to EGL, doesn't fully work yet but these changes
need to get off my hard disk
---

diff --git a/src/mesa/drivers/dri/radeon/server/radeon.h b/src/mesa/drivers/dri/radeon/server/radeon.h
index 7ffeec7..6f6c2e6 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon.h
+++ b/src/mesa/drivers/dri/radeon/server/radeon.h
@@ -52,6 +52,7 @@
 #       define RADEON_CSQ_PRIBM_INDBM          (4    << 28)
 #       define RADEON_CSQ_PRIPIO_INDPIO        (15   << 28)
 
+#define RADEON_PCIGART_TABLE_SIZE       32768
 
 #define PCI_CHIP_R200_BB                0x4242
 #define PCI_CHIP_RV250_Id               0x4964
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_egl.c b/src/mesa/drivers/dri/radeon/server/radeon_egl.c
index e567302..7b7057c 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon_egl.c
+++ b/src/mesa/drivers/dri/radeon/server/radeon_egl.c
@@ -342,13 +342,17 @@ RADEONMemoryInit(driDisplay *disp, RADEONInfoPtr info)
                               + RADEON_BUFFER_ALIGN)
                              & ~RADEON_BUFFER_ALIGN);
    int        l;
+   int        pcie_gart_table_size = 0;
 
    info->frontOffset = 0;
    info->frontPitch = disp->virtualWidth;
 
+   if (disp->card_type==RADEON_CARD_PCIE)
+     pcie_gart_table_size  = RADEON_PCIGART_TABLE_SIZE;
+
    /* Front, back and depth buffers - everything else texture??
     */
-   info->textureSize = disp->fbSize - 2 * bufferSize - depthSize;
+   info->textureSize = disp->fbSize - pcie_gart_table_size - 2 * bufferSize - depthSize;
 
    if (info->textureSize < 0)
       return 0;
@@ -372,7 +376,7 @@ RADEONMemoryInit(driDisplay *disp, RADEONInfoPtr info)
    }
 
    /* Reserve space for textures */
-   info->textureOffset = ((disp->fbSize - info->textureSize +
+   info->textureOffset = ((disp->fbSize - pcie_gart_table_size - info->textureSize +
                            RADEON_BUFFER_ALIGN) &
                           ~RADEON_BUFFER_ALIGN);
 
@@ -389,6 +393,8 @@ RADEONMemoryInit(driDisplay *disp, RADEONInfoPtr info)
                        ~RADEON_BUFFER_ALIGN);
    info->backPitch = disp->virtualWidth;
 
+   if (pcie_gart_table_size)
+     info->pcieGartTableOffset = disp->fbSize - pcie_gart_table_size;
 
    fprintf(stderr,
            "Will use back buffer at offset 0x%x, pitch %d\n",
@@ -399,6 +405,12 @@ RADEONMemoryInit(driDisplay *disp, RADEONInfoPtr info)
    fprintf(stderr,
            "Will use %d kb for textures at offset 0x%x\n",
            info->textureSize/1024, info->textureOffset);
+   if (pcie_gart_table_size)
+   { 
+     fprintf(stderr,
+	     "Will use %d kb for PCIE GART Table at offset 0x%x\n",
+	     pcie_gart_table_size/1024, info->pcieGartTableOffset);
+   }
 
    /* XXX I don't think these are needed. */
 #if 0
@@ -412,6 +424,9 @@ RADEONMemoryInit(driDisplay *disp, RADEONInfoPtr info)
                              (info->depthOffset >> 10));
 #endif
 
+   if (pcie_gart_table_size)
+     RADEONSetParam(disp, RADEON_SETPARAM_PCIGART_LOCATION, info->pcieGartTableOffset);
+
    return 1;
 }