From: Craig Topper <craig.topper@sifive.com>
Date: Tue, 30 May 2023 22:08:08 +0000 (-0700)
Subject: [RISCV] Allow FWMUL formation for an FP extend used twice by the same multiply.
X-Git-Tag: upstream/17.0.6~6755
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=454163354b0b2755746f9b3c32059adff4d34bd3;p=platform%2Fupstream%2Fllvm.git

[RISCV] Allow FWMUL formation for an FP extend used twice by the same multiply.
---

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 9d0267912c9f..229345159280 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -11372,7 +11372,8 @@ static SDValue performVFMUL_VLCombine(SDNode *N, SelectionDAG &DAG) {
 
   // TODO: Refactor to handle more complex cases similar to
   // combineBinOp_VLToVWBinOp_VL.
-  if (!Op0.hasOneUse() || !Op1.hasOneUse())
+  if ((!Op0.hasOneUse() || !Op1.hasOneUse()) &&
+      (Op0 != Op1 || !Op0->hasNUsesOfValue(2, 0)))
     return SDValue();
 
   // Check the mask and VL are the same.
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
index 83f6571bd325..c45349f975b5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
@@ -391,3 +391,44 @@ define <32 x double> @vfwmul_vf_v32f32(ptr %x, float %y) {
   %f = fmul <32 x double> %d, %e
   ret <32 x double> %f
 }
+
+define <2 x float> @vfwmul_squared_v2f16_v2f32(ptr %x) {
+; CHECK-LABEL: vfwmul_squared_v2f16_v2f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vle16.v v9, (a0)
+; CHECK-NEXT:    vfwmul.vv v8, v9, v9
+; CHECK-NEXT:    ret
+  %a = load <2 x half>, ptr %x
+  %b = fpext <2 x half> %a to <2 x float>
+  %c = fmul <2 x float> %b, %b
+  ret <2 x float> %c
+}
+
+define <2 x double> @vfwmul_squared_v2f32_v2f64(ptr %x) {
+; CHECK-LABEL: vfwmul_squared_v2f32_v2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT:    vle32.v v9, (a0)
+; CHECK-NEXT:    vfwmul.vv v8, v9, v9
+; CHECK-NEXT:    ret
+  %a = load <2 x float>, ptr %x
+  %b = fpext <2 x float> %a to <2 x double>
+  %c = fmul <2 x double> %b, %b
+  ret <2 x double> %c
+}
+
+define <2 x double> @vfwmul_squared_v2f16_v2f64(ptr %x) {
+; CHECK-LABEL: vfwmul_squared_v2f16_v2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vfwcvt.f.f.v v9, v8
+; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT:    vfwmul.vv v8, v9, v9
+; CHECK-NEXT:    ret
+  %a = load <2 x half>, ptr %x
+  %b = fpext <2 x half> %a to <2 x double>
+  %c = fmul <2 x double> %b, %b
+  ret <2 x double> %c
+}